Logic cell with improved multiplexer, barrel shifter, and crossbarring efficiency

A logic device comprising:

• a plurality of logic blocks, each of the plurality of logic blocks including:
• a first logic element (LE) including a first plurality of LE input terminals, a first LE output terminal of the first LE, and a second LE output terminal of the first LE;
• a second LE including a second plurality of LE input terminals, a first LE output terminal of the second LE, and a second LE output terminal of the second LE;
• a first multiplexer including a first plurality of multiplexer input terminals and a first select terminal, wherein a first multiplexer input terminal of the first plurality of multiplexer input terminals is coupled to the first LE output terminal of the first LE, a second multiplexer input terminal of the first plurality of multiplexer input terminals is coupled to the first LE output terminal of the second LE, and the first select terminal is coupled to a first select signal line;
• a second multiplexer including a second plurality of multiplexer input terminals and a second select terminal wherein a first multiplexer input terminal of the second plurality of multiplexer input terminals is coupled to the second LE output terminal of the first LE, a second multiplexer input terminal of the second plurality of multiplexer input terminals is coupled to the second LE output terminal of the second LE, and the second select teal is coupled to a second select signal line,
• a third LE including a third plurality of LE input terminals, a first LE output terminal of the third LE, and a second LE output terminal of the third LE;
• a third multiplexer including a third plurality of multiplexer input terminals and a third select terminal, wherein a first multiplexer input terminal of the third plurality of multiplexer input terminals is coupled to the first LE output terminal of the second LE, a second multiplexer input terminal of the third plurality of multiplexer input terminal is coupled to the first LE output terminal of the third LE, and the third select terminal is coupled to the first select signal line;
• and
• a fourth multiplexer including a fourth plurality of multiplexer input terminals and a fourth select terminal, wherein a first multiplexer input terminal of the fourth plurality of multiplexer input terminals is coupled to the second LE output terminal of the second LE, a second multiplexer input terminal of the fourth plurality of multiplexer input terminals is coupled to the second LE output terminal of the third LE, and the fourth select terminal is coupled to the second select signal line.

A method of multiplexing a plurality of data input signals in a logic block, the method comprising:

• receiving in the logic block a first plurality of data input signals of the plurality of data input signals on a first plurality of logic element (LE) input terminals of a first LE;
• multiplexing in the logic block the first plurality of data input signals in the first LE;
• receiving in the logic block a second plurality of data input signals of the plurality of data input signals on a first plurality of logic element (LE) input terminals of a second LE;
• multiplexing in the logic block the second plurality of data input signals in the second LE;
• multiplexing outputs of the first and second LEs in a first multiplexer, wherein the first multiplexer receives a select signal from an LE input terminal of the first LE;
• receiving in the logic block a third plurality of data input signals of the plurality of data input signals on a first plurality of LE input teals of a third LE;
• multiple in the logic block the third plurality of data input signals in the third LE;
• receiving in the logic block a fourth plurality of data input signals of the plurality of data input signals on a first plurality of LE input terminals of a fourth LE;
• and
• multiplexing in the logic block the fourth plural of data input signals in the fourth LE;
• and multiplexing outputs of the third and fourth LEs in a second multiplexer, wherein the second multiplexer receives a select signal from an LE input terminal of the third LE.

A method of multiplexing a plurality of data input signals, the method comprising:

• receiving a first plurality of data input signals of the plurality of data input signals on a first plurality of logic element (LE) input terminals of a first LE;
• first multiplexing the first plurality of data input signals in the first LE using a first set of select signals;
• second multiplexing the first plurality of data input signals in the first LE using a second set of select signals;
• receiving a second plurality of data input signals of the plurality of data input signals on a first plurality of LE input terminals of a second LE;
• first multiplexing the second plurality of data input signals in the second LE using a third set of select signals;
• second multiplexing the second plurality of data input signals in the second LE using a fourth set of select signals;
• multiplexing in a first multiplexer results of the first multiplexing in the first LE and of the first multiplexing in the second LE, wherein the first multiplexer receives a select signal from a first select signal line;
• and
• multiplexing in a second multiplexer results of the second multiplexing in the first LE and of the second multiplexing in the second LE, wherein the second multiplexer receives a select signal from a second select signal line.