Test structure design for reliability test
AssigneeApplied Materials, Inc.
InventorsNaomi Yoshida, Toshiyuki Nagata
Life of this patent
Estimating the term…
Abstract
A flexible semiconductor test structure that may be incorporated into a semiconductor device is provided. The test structure may include a plurality of test pads designed to physically stress conductive lines to which they are attached during thermal cycling. By utilizing test pads with different dimensions (lengths and/or widths), the effects of thermal stress generated by a plurality of conductive lines having corresponding different dimensions may be simulated.
Claims23
A test structure for determining the reliability of conductive lines formed in a semiconductor substrate, comprising:
- a conductive line formed in a first metal layer of the semiconductor substrate;
- one or more thermal stress-inducing test pads formed in a second metal layer of the semiconductor substrate, wherein each of the test pads is wider in at least two dimensions than a line width of the conductive line and is adapted to stress the conductive line to which the test pad is attached during thermal cycling;
- one or more vias electrically and mechanically coupling the one or more test pads to the conductive line;
- a plurality of probe contact pads electrically coupled to the conductive line at different locations, allowing the measurement of at least one of line resistance of the conductive line or the resistance across one or more of the vias;
- and
- one or more dielectric materials disposed between the metal layers.
A test structure for determining the reliability of conductive lines formed in a semiconductor substrate, comprising:
- a conductive line formed in a first metal layer of the semiconductor substrate;
- one or more thermal stress-inducing test pads formed in a second metal layer of the semiconductor substrate, wherein each of the test pads is wider in at least two dimensions than a line width of the conductive line, wherein the thermal stress-inducing test pads simulate the affect of thermal stress on the conductive line;
- one or more vias electrically and mechanically coupling the one or more test pads to the conductive line;
- a plurality of probe contact pads electrically coupled to the conductive line at different locations, allowing the measurement of at least one of line resistance of the conductive line or the resistance across one or more of the vias;
- and
- one or more dielectric materials disposed between the metal layers.
A test structure for determining the reliability of conductive lines formed in a semiconductor substrate, comprising:
- a conductive line formed in a first metal layer of the semiconductor substrate;
- one or more thermal stress-inducing test pads formed in a second metal layer of the semiconductor substrate, wherein each of the test pads is wider in at least two dimensions than a line width of the conductive line;
- one or more vias electrically and mechanically coupling the one or more test pads to the conductive line;
- a plurality of probe contact pads electrically coupled to the conductive line at different locations, allowing the measurement of at least one of line resistance of the conductive line or the resistance across one or more of the vias;
- one or more dielectric materials disposed between the metal layers;
- and
- a plurality of conductive dummy lines formed in the first metal layer adjacent the first conductive line, wherein the dummy lines are not coupled to test pads formed in the second metal layer.
Dependencies are inferred from the claim text.