Back to results
US 7,119,570 B1Granted
Method of measuring performance of a semiconductor device and circuit for the same
AssigneeXilinx, Inc.
InventorsManoj Chirania, Venu M. Kondapalli, Martin L. Voogel, Philip Costello
Life of this patent
Estimating the term…
Abstract
A test circuit to test rise delay/fall delay performance on a semiconductor device may comprise a latch to latch data at its input responsive to a clock signal. The latch may source an output signal related to the data latched. A buffer chain may be configured to serially propagate the signal sourced by the latch from the latch output back to the clock input, as the clock signal. A reset/set input of the latch may be configured to receive a reset/set signal from an intermediate node of the buffer chain.
Claims18
A circuit comprising:
- a latch to latch data at its input responsive to a clock signal and to source an output signal related to the data latched;
- the latch further comprising a reset/set input to receive a reset/set signal to clear/set the data latched;
- and
- a buffer chain disposed serially between an output of the latch and a clock input of the latch and operable to propagate the signal sourced by the latch;
- the buffer chain comprising:
- an intermediate node to source a reset/set signal to the reset/set input of the latch;
- a first group of buffers coupled in series between the output of the latch and the intermediate node;
- and
- a second group of buffers is coupled in series with the first group of buffers and disposed between the intermediate node and the clock input of the latch.
6 more elements
A circuit comprising:
- a latch to latch data at its input responsive to a clock signal and to source an output signal related to the data latched;
- the latch further comprising a reset/set input to receive a reset/set signal to clear/set the data latched;
- a buffer chain disposed serially between an output of the latch and a clock input of the latch and operable to propagate the signal sourced by the latch;
- the buffer chain comprising:
- an intermediate node to source a reset/set signal to the reset/set input of the latch;
- a first group of buffers coupled in series between the output of the latch and the intermediate node;
- and
- a second group of buffers coupled in series with the first group and disposed between the intermediate node and the clock input of the latch;
- switching circuitry selectably operable to propagate the reset/set signal to one of the reset and set inputs of the latch dependent on a control signal;
- and
- an inverter selectably and removeably operable in series between the buffer chain and the clock input dependent on the control signal.
8 more elements
A circuit comprising:
- a latch to latch data at its input responsive to a clock signal and to source an output signal related to the data latched;
- the latch further comprising a reset/set input to receive a reset/set signal to clear/set the data latched;
- a buffer chain disposed serially between an output of the latch and a clock input of the latch and operable to propagate the signal sourced by the latch;
- the buffer chain comprising an intermediate node to source a reset/set signal to the reset/set input of the latch;
- measurement means for determining an oscillation frequency associated with the latch and the buffer;
- and
- grading means for grading product dependent on the oscillation frequency determined by the measurement means.
4 more elements
Dependencies are inferred from the claim text.