Chip carrier and method for testing electrical performance of passive component

A method for testing electrical performance of a passive component, for use with a chip carrier having a core layer on which a plurality of conductive traces are formed, the conductive traces comprising at least one first trace predetermined to be connected with the passive component, the method comprising the steps of:

• setting a first predetermined position on the first trace, and allowing two ends of the first trace to be respectively electrically connected to a first bond finger formed on a surface, mounted with the passive component, of the chip carrier, and to a first ball pad formed on an opposite surface of the chip carrier, wherein the first predetermined position and the first bond finger are located on the same side relative to the passive component;
• setting a second trace from the plurality of conductive traces and a second predetermined position on the second trace, wherein the second trace is predetermined free of connection with the passive component, and one end of the second trace is connected to a second ball pad formed on the same surface as the first ball pad;
• applying a solder mask layer over the conductive traces and forming a plurality of openings through the solder mask layer for at least exposing the first predetermined position and the second predetermined position;
• mounting the passive component on the first trace;
• interconnecting the first predetermined position and second predetermined position via an electrically conductive material;
• and
• contacting two test heads respectively with the first ball pad and second ball pad, which are situated on the same surface of the chip carrier, to testing the electrical performance of the passive component.