US 7,119,420 B2Granted

Chip packaging structure adapted to reduce electromagnetic interference

AssigneeDomintech Co., Ltd.

InventorChung-Hsing Tzu

Life of this patent

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Abstract

A chip packaging structure adapted to reduce EMI includes a chip having contacts provided on one side thereof, and a leadframe having a plurality of leads arranged in a predetermined manner and provided at a bottom side with a conducting protrusion each for electrically connecting to external elements. The leadframe is fixedly attached to one side of the chip having the contacts provided thereon, and the leads are electrically connected at inner ends to the contacts via lead wires. An adhesive layer is applied to one side of the leadframe having the protrusions to thereby adhere a conducting layer to the leadframe with the protrusions downward extended through multiple through holes on the conducting layer; and at least one of the contacts on the chip is electrically connected to the conducting layer for the latter to serve as a ground or a power plane.

Claims6

Dependent claims

A chip packaging structure adapted to reduce electromagnetic interference, comprising a chip having a plurality of electrical contacts provided on one side thereof, and a leadframe having a plurality of leads that are arranged in a predetermined manner and provided at one side with a protrusion each for electrically connecting to external elements;

said chip packaging structure being characterized in that said leadframe are fixedly attached to the side of said chip having said electrical contacts provided thereon, such that said protrusions on said leads of said leadframe are located closer to lateral outer sides of said leadframe;
that said leads are connected at respective inner ends to said electrical contacts on said chip via lead wires;
that an adhesive layer is applied to one side of said leadframe having said protrusions provided thereon to thereby adhere a conducting layer in the form of a sheet to said leadframe with said protrusions on said leads downward extended through multiple rows of through holes formed on said conducting layer corresponding to said protrusions on said leads;
and that at least one of said electrical contacts on said chip is electrically connected to said conducting layer.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 11/165,170Filed 24 Jun 2005
Priority: TW 94201846 U1 Feb 2005
Published: US 2006/0170082 A13 Aug 2006
Granted: 10 Oct 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10W 42/20
Arrangements for protection of devices: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
H10W 70/415
Chip-supporting parts, e.g. die pads: leadframe inner leads serving as die pads
H10W 72/00
Interconnections or connectors in packages
H10W 74/129
The semiconductor body being completely enclosed: forming a chip-scale package [CSP]