Semiconductor device and method for fabricating the same

A semiconductor device having a first MIS transistor provided in a semiconductor layer,

• wherein the first MIS transistor comprises:
• a first gate insulating film provided on the semiconductor layer;
• a first gate electrode provided on the first gate insulating film;
• first extension regions containing a first dopant of a first conductivity type and provided in regions of the semiconductor layer located below sides of the first gate electrode, respectively;
• dopant regions containing a second dopant of the first conductivity type and provided in regions of the semiconductor layer located below the sides of the first gate electrode and deeper than the first extension region, respectively;
• nitrogen diffusion layers provided on the first extension regions and in an upper surface portion of the semiconductor layer, respectively;
• a sidewall provided on each side surface of the first gate electrode;
• and
• source and drain regions containing a third dopant of the first conductivity type and each provided in a region of the semiconductor layer located below a corresponding side of the sidewall,
• wherein the sidewall comprises:
• a first sidewall provided on a corresponding side surface of the first gate electrode;
• and a second sidewall provided to the corresponding side surface of the first gate electrode with the first sidewall interposed therebetween.

A semiconductor device having a first MIS transistor provided in a semiconductor layer,

• wherein the first MIS transistor comprises:
• a first gate insulating film provided on the semiconductor layer;
• a first gate electrode provided on the first gate insulating film;
• first extension regions containing a first dopant of a first conductivity type and provided in regions of the semiconductor layer located below sides of the first gate electrode, respectively;
• dopant regions containing a second dopant of the first conductivity type and provided in regions of the semiconductor layer located below the sides of the first gate electrode and deeper than the first extension region, respectively;
• and
• nitrogen diffusion layers provided on the first extension regions and in an upper surface portion of the semiconductor layer, respectively,
• wherein a second MIS transistor is provided in a region of the semiconductor layer differing from the region where the first MIS transistor is provided, and
• the second MIS transistor comprises:
• a second gate insulating film provided on the semiconductor layer;
• a second gate electrode provided on the second gate insulating film;
• second extension regions containing a fourth dopant of the first conductivity type and provided in regions of the semiconductor layer located below sides of the second gate electrode, respectively;
• and
• pocket regions containing a dopant of a second conductivity type and provided in regions of the semiconductor layer located below the sides of the second gate electrode and deeper than the second extension regions, respectively.