High performance strained channel MOSFETs by coupled stress effects
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng-Hung Chang, Weng Chang, Chu-Yun Fu
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Abstract
Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strained shallow trench isolation regions in the semiconductor substrate; forming PMOS and NMOS devices on the semiconductor substrate including doped source and drain regions; forming a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices; and, forming a tensile strained dielectric insulating layer over the CESL layer.
Claims27
A strained channel transistor pair comprising:
- a semiconductor substrate comprising tensile strained shallow trench isolation structures adjacent respective active areas for forming PMOS and NMOS devices;
- the PMOS and NMOS devices on the respective active areas, each of said PMOS and NMOS devices comprising doped source and drain regions disposed in the semiconductor substrate adjacent each of said PMOS and NMOS devices;
- compressive strained salicides on the doped source and drain regions;
- a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices;
- and,
- a tensile strained dielectric insulating layer on the CESL layer.
A strained channel NMOS and PMOS device pair with improved NMOS performance without substantially degrading PMOS device performance comprising:
- a semiconductor substrate comprising tensile strained shallow trench isolation structures adjacent respective active areas for forming PMOS and NMOS devices;
- the PMOS and NMOS devices on the respective active areas, each of said PMOS and NMOS devices comprising doped source and drain regions disposed in the semiconductor substrate adjacent each of said PMOS and NMOS devices;
- compressive strained salicides on the source and drain regions;
- a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices;
- and,
- a tensile strained dielectric insulating layer on the CESL layer.
A strained channel NMOS and PMOS device pair for improving NMOS performance without substantially degrading PMOS device performance comprising:
- a semiconductor substrate comprising tensile strained shallow trench isolation structures adjacent respective active areas comprising PMOS and NMOS devices;
- each of said PMOS and NMOS devices comprising doped source and drain regions disposed in the semiconductor substrate adjacent each of said PMOS and NMOS devices;
- compressive strained salicides on the source and drain regions;
- and,
- wherein a tensile strained contact etching stop layer (CESL) is disposed over both the PMOS and NMOS devices.
Dependencies are inferred from the claim text.