High performance strained CMOS devices
AssigneeInternational Business Machines Corporation
InventorsBruce B. Doris, Oleg G. Gluschenkov
Life of this patent
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Abstract
A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si—SiO2 interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si—SiO2 interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.
Claims16
A semiconductor structure formed on a substrate, comprising:
- an n-channel field effect transistor having a source, a drain, a gate, and a direction of current flow from the source to the drain;
- a first shallow trench isolation for the n-channel field effect transistor comprising a first shallow trench isolation side, the first shallow trench isolation side having at least one overhang configured to prevent oxidation induced stress in a direction parallel to the direction of current flow for the n-channel field effect transistor,
- the first shallow trench isolation for the n-channel field effect transistor further comprising a second shallow trench isolation side being transverse to the first shallow trench isolation side and having at least one overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow for the n-channel field effect transistor;
- a p-channel field effect transistor, the p-channel field effect transistor having a source, a drain, a gate, and a direction of current flow from the source to the drain;
- a second shallow trench isolation for the p-channel field effect transistor having a third shallow trench isolation side, the third shallow trench isolation side being devoid of an overhang;
- and
- the second shallow trench isolation for the p-channel field effect transistor further having a fourth shallow trench isolation side, the fourth shallow trench isolation side being transverse to the third shallow trench isolation side and having at least one overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow for the p-channel field effect transistor.
A semiconductor structure, comprising:
- an first transistor having a first shallow trench isolation having:
- a side with at least one overhang configured to prevent oxidation induced stress in a direction parallel to a direction of current flow;
- and
- a transverse side having at least one overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow for the first transistor;
- a second transistor with a shallow trench isolation having:
- a side devoid of an overhang;
- and
- a traverse side having at least one overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow for the second transistor, wherein
- the at least one overhang of the first transistor and the second transistor are provided when a distance between an STI and one of the first transistor and the second transistor is less than or equal to a predetermined distance which varies based on at least one of thermal mismatch between isolation, dielectric and silicon substrate and intrinsic stress of a nitride mask used to form the semiconductor structure.
Dependencies are inferred from the claim text.