Field effect transistor and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsAtsuhiro Kinoshita, Junji Koga
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Abstract
A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.
Claims5
A field effect transistor comprising:
- a first semiconductor region forming a channel region,
- a gate electrode insulatively disposed above the first semiconductor region,
- a source electrode and a drain electrode which are formed, respectively, on both sides of the first semiconductor region in a position corresponding to the gate electrode, and
- second semiconductor regions each formed between the first semiconductor region and a corresponding one of the source electrode and the drain electrode, and having a higher impurity concentration than the first semiconductor region,
- wherein the second semiconductor regions have an impurity concentration N that is at least 4×1019 cm−3, and a distance Ws between a lower surface of the gate electrode and each of the source electrode and the drain electrode is given by;
- Ws≦2×(εs·Eg/q·N)1/2
- where εs is a dielectric constant of the second semiconductor regions and q is an elementary charge.
Dependencies are inferred from the claim text.