LDMOS transistor
AssigneeInfineon Technologies AG
InventorsGordon Ma, Carsten Ahrens
Life of this patent
Estimating the term…
Abstract
A semiconductor device has a semiconductor substrate, an insulating layer on top of the substrate, a lateral field effect transistor with a drain region and a source region arranged in the substrate and a gate arranged above the substrate within the insulating layer, a drain runner arranged on top of the insulator layer above the drain region, a source runner arranged on top of the insulator layer above the source region, a gate runner arranged on top of the insulator layer outside an area defined by the drain runner and the source runner, a first coupling structure with a via for coupling the drain runner with the drain region, and a second coupling structure with a via for coupling the source runner with the source region.
Claims26
A Semiconductor device comprising:
- a semiconductor substrate,
- an insulating layer on top of said substrate,
- a lateral field effect transistor comprising a drain region and a source region arranged in said substrate and a gate arranged above said substrate within said insulating layer,
- a drain runner arranged on top of the insulator layer above said drain region,
- a source runner arranged on top of the insulator layer above said source region,
- a gate runner arranged on top of the insulator layer outside an area defined by said drain runner and said source runner,
- a first coupling structure comprising a via for coupling said drain runner with said drain region, and
- a second coupling structure comprising a via for coupling said source runner with said source region and a barrier metal layer arranged at the bottom of said via and within said insulating layer, wherein the barrier metal layer comprises a first horizontal bottom layer adjacent said via and a side wall being rectangular to and surrounding said first horizontal bottom layer and said side wall is spaced apart from said via.
A Semiconductor device comprising:
- a semiconductor substrate,
- an insulator layer on top of said substrate,
- a lateral field effect transistor comprising a drain region and a source region arranged in said substrate and a gate arranged above said substrate within said insulator layer,
- a drain runner arranged in said insulator layer above said drain region,
- a source runner arranged in said insulator layer above said source region,
- a gate runner arranged in said insulator layer outside an area defined by said drain runner and said source runner,
- a first coupling structure comprising a via for coupling said drain runner with said drain region,
- a second coupling structure comprising a via for coupling said source runner with said source region and a barrier metal layers arranged at the bottom of said via and within said insulating layer, wherein the barrier metal layer comprises a first horizontal bottom layer adjacent said via and a side wall being rectangular to and surrounding said first horizontal bottom layer and said side wall is spaced apart from said via,
- wherein said first and second coupling structure further comprise barrier metal layers arranged at the top and the bottom of said via,
- a sinker structure that reaches from the top to the bottom of said substrate, and
- a backside metal layer arranged on the bottom surface of said substrate.
Dependencies are inferred from the claim text.