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AssigneeMicron Technology, Inc.
InventorsMark Fischer, Charles H. Dennison, Fawad Ahmed, Richard H. Lane, John K. Zahurak, Kunal R. Parekh
Estimating the term…
A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
An integrated circuit, comprising:
A semiconductor device comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Characterised by the semiconductor materials: into Group IV semiconductors
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers
Of electrically active species: through-implantation
Term ended 21 Mar 2020 (estimated)
1. Field of the Invention
The present invention relates to the field of semiconductor memory devices and, more particularly to a structure having improved static refresh properties in dynamic random access memory devices and a method of making it.
2. Description of the Related Art
The foregoing and other advantages and features of the invention will become more apparent from the detailed description of the preferred embodiments of the invention given below with reference to the accompanying drawings in which:
FIG. 1 is a fragmentary vertical cross-sectional view of a prior art memory array device conventional diffusion regions;
FIG. 2 is a fragmentary vertical cross sectional view of an integrated circuit memory array device formed in accordance with the present invention;
The present invention will be described as set forth in the preferred embodiments illustrated in FIGS. 2–7 and 11. Other embodiments may be utilized and structural or logical changes may be made without departing from the spirit or scope of the present invention. Like items are referred to by like reference numerals.
FIG. 2 illustrates a portion of an integrated circuit MOSFET memory array device 105 constructed in accordance with the present invention. The device 105 is preferably used as an access device of a DRAM memory cell. As will be described with reference to FIGS. 3 to 7, the device 105 including diffusion regions 130, 132 is fabricated using two blanket phosphorous ion implant steps sandwiched around a conventional re-ox step. Since two implant steps are performed, diffusion region 130 comprises two regions 130a, 130b having different dopant concentrations. Similarly, diffusion region 132 comprises two regions 132a, 132b having different dopant concentrations. As described with reference to FIGS. 9 and 10, the uniquely formed diffusion regions 130, 132 provide the device 105 with improved static refresh performance over the prior device 5 (illustrated in FIG. 1). Since the method uses two separate blanket phosphorous ion implant steps, it will be referred to hereinafter as a “double blanket ion implant method.”
Hereinafter, the terms “wafer” and “substrate” are used interchangeably and are to be, understood as including silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation.