Dynamic random access memory and fabrication thereof
AssigneeProMOS Technologies Inc.
InventorTing-Shing Wang
Life of this patent
Estimating the term…
Abstract
A dynamic random access memory (DRAM) cell is described, including a semiconductor pillar on a substrate, a capacitor on a lower portion of a sidewall of the pillar, and a vertical transistor on an upper portion of the sidewall of the pillar. The capacitor includes a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at the periphery of the first plate, a third plate at the periphery of the second plate electrically connected with the first plate to form a lower electrode, and a dielectric layer separating the second plate from the first and third plates. A DRAM array based on the DRAM cell and a method for fabricating the DRAM array are also described.
Claims22
A dynamic random access memory (DRAM) cell, comprising:
- a semiconductor pillar on a substrate;
- a capacitor on a lower portion of a sidewall of the pillar, comprising:
- a first plate in the lower portion of the sidewall of the pillar;
- a second plate as an upper electrode at periphery of the first plate;
- a third plate at periphery of the second plate, electrically connecting wit the first plate to form a lower electrode together;
- and
- a dielectric layer, separating the second plate from the first plate and the third plate;
- and
- a vertical transistor on an upper portion of the sidewall of the pillar, electrically coupled with the capacitor.
A dynamic random access memory (DRAM) array, comprising:
- rows and columns of memory cells disposed on a substrate, each comprising:
- a semiconductor pillar on the substrate;
- a capacitor on a lower portion of a sidewall of the pillar, comprising a first plate in the lower portion of the sidewall of the pillar, a second plate as an upper electrode at periphery of the first plate, a third plate disposed at periphery of the second plate and electrically connected with the first plate to form a lower electrode together and a dielectric layer separating the second plate from the first plate and the third plate;
- and
- a vertical transistor on an upper portion of the sidewall of the pillar, electrically coupled with the capacitor;
- a plurality of bit lines, each coupled with one row of vertical transistors;
- and
- a plurality of word lines, each coupled with one column of vertical transistors.
Dependencies are inferred from the claim text.