Dynamic random access memory cells having laterally offset storage nodes

A DRAM cell array region comprising:

• a plurality of active regions comprising first active regions and second active regions which are two dimensionally arrayed in a semiconductor substrate along rows and columns, the first active regions having a first pitch and a second pitch along an x-axis parallel to the rows and a y-axis parallel to the columns respectively, the second active regions being disposed at positions such that the first active regions are parallel-shifted by a half of the first pitch and a half of the second pitch along the x-axis and the y-axis respectively, and the active regions being defined by an isolation layer;
• a first and a second MOS transistor in each of the first active regions and serially connected to each other, the fast MOS transistor having a first impurity region at one end of the first active region to act as a source region of the first MOS transistor and the second MOS transistor having a second impurity region at another end of the first active region to act as a source region of the second MOS transistor;
• a third MOS transistor and a fourth MOS transistor in each of the second active regions and serially connected to each other, the third MOS transistor having a third impurity region at one end of the second active region to act as a source region of the third MOS transistor and the fourth MOS transistor having a fourth impurity region at another end of the second active region to act as a source region of the fourth MOS transistor;
• and
• first through fourth storage nodes disposed on the substrate having the first through fourth MOS transistors, the first and second storage nodes being electrically connected to the first and second impurity regions, respectively, and the third and fourth storage nodes being electrically connected to the third and fourth impurity regions, respectively, central axes of the first and second storage nodes passing through a first position and a second position that are spaced apart from central points of the first and second impurity regions toward a negative direction of the x-axis by a first and a second predetermined distances, respectively, and central axes of the third and fourth storage nodes passing through a third position and a fourth position that are spaced apart from central points of the third and fourth impurity regions toward a positive direction of the x-axis by a third and a fourth predetermined distances, respectively.

A DRAM cell array region comprising:

• a common drain region in an integrated circuit substrate;
• first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions;
• and
• first and second storage nodes on the integrated circuit substrate, a respective one of which is electrically connected to a respective one of the first and second source regions, the first and second storage nodes being laterally offset from the respective first and second source regions along the first direction, such that the first and second storage nodes are not laterally offset from the respective first and second source regions toward one another or away from one another.

A DRAM cell array region comprising:

• a plurality of equally spaced apart alternating rows of first and second active regions in an integrated circuit substrate, the second active regions being laterally offset from the first active regions such that a respective second active region is equally spaced apart from two closest first active regions in an adjacent row;
• each of the first active regions comprising first and second source regions and a first common drain region therebetween, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions;
• each of the second active regions comprising third and fourth source regions and a second common drain region therebetween, a respective one of which is laterally offset from the second common drain region along the respective first and second opposite directions;
• an may of first and second storage nodes on the integrated circuit substrate, a respective one of the first and second storage nodes being electrically connected to a respective one of the first and second source regions, the respective first and second storage nodes being laterally offset from the respective first and second source regions along the first direction;
• and
• an array of third and fourth storage nodes on the integrated circuit substrate, a respective one of the third and fourth storage nodes being electrically connected to a respective one of the third and fourth source regions, the respective third and fourth storage nodes being laterally offset from the respective third and fourth source regions along the second direction.