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US 7,119,369 B2Granted
FET having epitaxial silicon growth
AssigneeMicro Technology, Inc.
InventorsZhongze Wang, Chih-Chen Cho, Er-Xuan Ping
Life of this patent
Estimating the term…
Abstract
A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region.
Claims57
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath only a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath only a portion of the second source/drain region;
- wherein the first and second source/drain regions each comprise polysilicon interposed between the extension of epitaxial silicon and the corresponding field isolation region.
5 more elements
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region;
- wherein the bulk semiconductor substrate comprises monocrystalline silicon having a first conductivity type, the source/drain regions comprise polysilicon having a second conductivity type opposite the first conductivity type, and the extensions of epitaxial silicon comprise epitaxial silicon having a conductivity type.
5 more elements
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region and having a polycrystalline portion;
- a second source/drain region on a second side of the channel region and having a polycrystalline portion;
- first and second extensions of epitaxial silicon formed on the bulk semiconductor substrate, the first and second extensions of epitaxial silicon respectively extending away from the first and second sides of the first channel region, the first extension of epitaxial silicon interposed between the first side of the channel region and the polysilicon portion of the first source/drain region and the second extension of epitaxial silicon interposed between the second side of the channel region and the polysilicon portion of the second source/drain region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region and extending beneath at least a portion of the first extension of epitaxial silicon;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region and extending beneath at least a portion of the second extension of epitaxial silicon.
4 more elements
A field-effect transistor, comprising:
- a channel region in a monocrystalline silicon substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- epitaxial silicon formed on the monocrystalline silicon substrate so as to extend away from each side of the channel region;
- and
- a gate overlying the channel region;
- wherein the monocrystalline silicon substrate comprises monocrystalline silicon having a first conductivity type, the source/drain regions comprise polysilicon having a second conductivity type opposite the first conductivity type, and the epitaxial silicon has a conductivity type.
4 more elements
A field-effect transistor, comprising:
- a channel region in a monocrystalline silicon substrate;
- a first source/drain region on a first side of the channel region and having a polycrystalline portion;
- a second source/drain region on a second side of the channel region and having a polycrystalline portion;
- epitaxial silicon interposed between the channel region and the polycrystalline portion of each source/drain region;
- and
- a gate overlying the channel region.
3 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region;
- wherein the first and second source/drain regions each comprise polysilicon interposed between the extension of epitaxial silicon and the corresponding field isolation region.
10 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region;
- wherein the bulk semiconductor substrate comprises monocrystalline silicon having a first conductivity type, the source/drain regions comprise polysilicon having a second conductivity type opposite the first conductivity type, and the extensions of epitaxial silicon comprise epitaxial silicon having a conductivity type.
10 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- first and second extensions of epitaxial silicon formed on the bulk semiconductor substrate, the first and second extensions of epitaxial silicon respectively extending away from the first and second sides of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region and extending beneath at least a portion of the first extension of epitaxial silicon;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region and extending beneath at least a portion of the second extension of epitaxial silicon.
- wherein the first and second source/drain regions each comprise polysilicon interposed between the extension of epitaxial silicon and the corresponding field isolation region.
10 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor the first and second source/drain regions each having a polysilicon portion;
- wherein the access transistor further comprises:
- a channel region in a monocrystalline silicon substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- and
- epitaxial silicon formed on the monocrystalline silicon substrate so as to extend away from each side of the channel region wherein the epitaxial silicon is interposed between the first side of the channel region and the polysilicon portion of the first source/drain region and between the second side of the channel region and the polysilicon portion of the second source/drain region.
7 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second polycrystalline source/drain region coupled to the capacitor, each of the first and second source/drain regions having a polycrystalline silicon portion;
- wherein the access transistor further comprises:
- a channel region in a monocrystalline silicon substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- and
- epitaxial silicon interposed between the channel region and the polycrystalline silicon portion of each source/drain region.
7 more elements
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- an extension of silicon-germanium alloy formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region.
- wherein the first and second source/drain regions each comprise polysilicon interposed between the extension of epitaxilal silicon and the corresponding field isolation region.
5 more elements
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- an extension of silicon-germanium alloy formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region;
- wherein the bulk semiconductor substrate comprises monocrystalline silicon having a first conductivity type, the source/drain regions comprise polysilicon having a second conductivity type opposite the first conductivity type, and the extensions of silicon-germanium alloy comprise silicon-germanium alloy having a conductivity type.
5 more elements
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- first and second extensions of silicon-germanium alloy formed on the bulk semiconductor substrate, the first and second extensions of silicon-germanium alloy respectively extending away from the first and second sides of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region and extending beneath only a portion of the first extension of silicon-germanium alloy;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region and extending beneath only a portion of the second extension of silicon-germanium alloy;
- wherein the first and second source/drain regions each comprise polysilicon interposed between the extension of epitaxial silicon and the corresponding field isolation region.
5 more elements
A field-effect transistor, comprising:
- a channel region in a monocrystalline silicon substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- epitaxial silicon-germanium alloy formed on the monocrystalline silicon substrate so as to extend away from each side of the channel region;
- and
- a gate overlying the channel region;
- wherein the monocrystalline silicon substrate comprises monocrystalline silicon having a first conductivity type, the source/drain regions comprise polysilicon having a second conductivity type opposite the first conductivity type, and the epitaxial silicon-germanium alloy has a conductivity type.
4 more elements
A field-effect transistor, comprising:
- a channel region in a monocrystalline silicon substrate;
- a first source/drain region on a first side of the channel region and having a polycrystalline portion;
- a second polycrystalline silicon source/drain region on a second side of the channel region and having a polycrystalline portion;
- epitaxial silicon-germanium alloy interposed between the channel region and the polycrystalline portion of each source/drain region;
- and
- a gate overlying the channel region.
3 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon-germanium alloy formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath only a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath only a portion of the second source/drain region;
- wherein the first and second source/drain regions each comprise polysilicon interposed between the extension of epitaxial silicon and the corresponding field isolation region.
10 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon-germanium alloy formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region;
- wherein the bulk semiconductor substrate comprises monocrystalline silicon having a first conductivity type, the source/drain regions comprise polysilicon having a second conductivity type opposite the first conductivity type, and the extensions of silicon-germanium alloy comprise silicon-germanium alloy having a conductivity type.
10 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- first and second extensions of epitaxial silicon-germanium alloy formed on the bulk semiconductor substrate, the first and second extensions of epitaxial silicon-germanium alloy respectively extending away from the first and second sides of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region and extending beneath only a portion of the first extension of epitaxial silicon-germanium alloy;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region and extending beneath only a portion of the second extension of epitaxial silicon-germanium alloy;
- wherein the first and second source/drain regions each comprise polysilicon interposed between the extension of epitaxial silicon and the corresponding field isolation region.
10 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a monocrystalline silicon substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- and
- epitaxial silicon-germanium alloy formed on the monocrystalline silicon substrate so as to extend away from each side of the channel region;
- wherein the monocrystalline silicon substrate comprises monocrystalline silicon having a first conductivity type, the source/drain regions comprise polysilicon having a second conductivity type opposite the first conductivity type, and the epitaxial silicon-germanium alloy has a conductivity type.
8 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first polycrystalline silicon source/drain region coupled to a bit line and a second polycrystalline source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a monocrystalline silicon substrate with the first polycrystalline silicon source/drain region on a first side of the channel region and the second polycrystalline silicon source/drain region on a second side of the channel region;
- and
- epitaxial silicon-germanium alloy formed on the monocrystalline silicon substrate so as to extend away from each side of the channel region.
7 more elements
An electronic system comprising:
- a processor;
- a memory device coupled to the processor, the memory device comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath only a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath only a portion of the second source/drain region a field isolation region laterally adjoining the second source/drain region and extending beneath only a portion of the second source/drain region;
- wherein the first and second source/drain regions each comprise polysilicon interposed between the extension of epitaxial silicon and the corresponding field isolation region.
12 more elements
An electronic system comprising:
- a processor;
- a memory device coupled to the processor, the memory device comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath at least a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath at least a portion of the second source/drain region;
- wherein the bulk semiconductor substrate comprises monocrystalline silicon having a first conductivity type, the source/drain regions comprise polysilicon having a second conductivity type opposite the first conductivity type, and the extensions of epitaxial silicon comprise epitaxial silicon having a conductivity type.
12 more elements
An electronic system comprising:
- a processor;
- a memory device coupled to the processor, the memory device comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- an extension of epitaxial silicon-germanium alloy formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- a field isolation region laterally adjoining the first source/drain region and extending beneath only a portion of the first source/drain region;
- and
- a field isolation region laterally adjoining the second source/drain region and extending beneath only a portion of the second source/drain region;
- wherein the first and second source/drain regions each comprise polysilicon interposed between the extension of epitaxial silicon and the corresponding field isolation region.
12 more elements
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region and having a polysilicon portion;
- a second source/drain region on a second side of the channel region and having a polysilicon portion;
- and
- an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region, wherein a first extension of epitaxial monocrystalline material is interposed between the first side of the channel region and the polysilicon portion of the first source/drain region and a second extension of epitaxial monocrystalline material is interposed between the second side of the channel region and the polysilicon portion of the second source/drain region.
2 more elements
A field-effect transistor, comprising:
- a channel region in a bulk semiconductor substrate;
- a first source/drain region on a first side of the channel region;
- a second source/drain region on a second side of the channel region;
- and
- an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region;
- wherein the bulk semiconductor substrate comprises monocrystalline silicon having a first conductivity type, the source/drain regions comprise polysilicon having a second conductivity type opposite the first conductivity type, and the extensions of epitaxial monocrystalline material comprise epitaxial silicon having a conductivity type.
3 more elements
A memory device, comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor, the first and second source/drain regions each comprising a polysilicon portion;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- and
- an epitaxial monocrystalline material formed on the bulk semiconductor substrate and interposed between the channel region and the polysilicon portions of the first and second source/drain regions.
7 more elements
An electronic system comprising:
- a processor;
- a memory device coupled to the processor, the memory device comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, wherein each memory cell comprises:
- a capacitor;
- and
- an access transistor having a gate coupled to a word line, a first source/drain region coupled to a bit line and a second source/drain region coupled to the capacitor, the first and second source/drain regions each comprising a polysilicon portion;
- wherein the access transistor further comprises:
- a channel region in a bulk semiconductor substrate with the first source/drain region on a first side of the channel region and the second source/drain region on a second side of the channel region;
- and
- an epitaxial monocrystalline material formed on the bulk semiconductor substrate and interposed between the channel region and the polysilicon portions of the first and second source/drain regions.
9 more elements
Dependencies are inferred from the claim text.