Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device

A method used to form a semiconductor device, comprising:

• providing a blanket polysilicon word line layer and at least one dielectric layer on the word line layer;
• using a single mask, etching the word line layer and the at least one dielectric layer to define a plurality of transistor word lines;
• forming a blanket polysilicon plug layer over the plurality of transistor word lines and over the at least one dielectric layer;
• planarizing the blanket polysilicon plug layer to remove the plug layer from over the plurality of transistor word lines to form a plurality of polysilicon plugs and to expose the at least one dielectric layer;
• subsequent to forming the plurality of polysilicon plugs, using an etch selective to polysilicon to remove the at least one dielectric layer from over the plurality of transistor word lines and to expose the plurality of transistor word lines;
• and
• forming a self-aligned silicide layer which simultaneously forms on the plurality of transistor word lines and on the plurality of plugs.

A method used to form a semiconductor device, comprising:

• forming a blanket conductive transistor word line layer over a semiconductor wafer substrate assembly;
• forming a blanket dielectric layer on the transistor word line layer;
• forming a patterned mask over the blanket dielectric layer and over the blanket conductive transistor word line layer;
• patterning the blanket dielectric layer and the blanket conductive transistor word line layer using the patterned mask to form a patterned dielectric layer from the blanket dielectric layer and a plurality of transistor word lines from the blanket conductive word line layer;
• forming a blanket conductive plug layer over the patterned dielectric layer, over the transistor word lines, and between adjacent transistor word lines;
• removing a portion of the blanket conductive plug layer by planarizing the blanket conductive plug layer in the absence of a mask layer to form a plurality of conductive plugs;
• subsequent to planarizing the blanket conductive plug layer, removing the patterned dielectric layer in the absence of a mask layer to expose the plurality of transistor word lines;
• subsequent to removing the patterned dielectric layer, forming a blanket metal layer on the plurality of conductive plugs, the plurality of transistor word lines, and on exposed dielectric layers;
• converting the metal layer on the conductive plugs and on the transistor word lines to an enhancement layer, while the metal layer on the exposed dielectric layers remains unconverted;
• and
• removing the unconverted portion of the metal layer in the absence of a mask layer and leaving the enhancement layer.

A method used during fabrication of a semiconductor device, comprising:

• forming at least one polysilicon transistor control gate layer over a semiconductor wafer substrate assembly;
• forming a silicon dioxide buffer layer on the at least one polysilicon transistor control gate layer, wherein the silicon dioxide buffer layer has an upper surface;
• etching the at least one polysilicon transistor control gate layer to define at least one polysilicon transistor control gate having first and second sidewalls and an upper surface;
• forming a first silicon nitride spacer along the first sidewall of the at least one polysilicon transistor control gate and a second silicon nitride spacer along the second sidewall of the at least one polysilicon transistor control gate, wherein an upper surface of each spacer extends above the upper surface of the at least one polysilicon transistor control gate but does not extend above the upper surface of the silicon dioxide buffer layer;
• forming a polysilicon plug layer over the silicon dioxide buffer layer;
• planarizing the polysilicon plug layer to expose the silicon dioxide buffer layer;
• etching the silicon dioxide buffer layer with an etch which is selective to the silicon nitride spacers to expose the at least one polysilicon transistor control gate;
• forming a metal layer on the polysilicon plug layer, on the at least one polysilicon transistor control gate, and on the first and second silicon nitride spacers;
• exposing the metal layer to an environment which reacts the metal layer with the polysilicon plug layer and with the at least one polysilicon transistor control gate to form a metal silicide, wherein the metal layer formed on the first and second silicon nitride spacers remains unreacted;
• and
• removing the unreacted metal from the silicon nitride spacers.

A method for forming a semiconductor device, comprising:

• forming a first conductive layer, a first silicon dioxide layer on the first conductive layer, a silicon nitride layer on the first silicon dioxide layer, and a second silicon dioxide layer on the silicon nitride layer;
• forming a patterned mask layer over the first silicon dioxide layer and over the first conductive layer;
• etching the second silicon dioxide layer, the silicon nitride layer, the first silicon dioxide layer, and the first conductive layer using the mask as a pattern to form first and second cross-sectional sidewalls from the second silicon dioxide layer, the silicon nitride layer, the first silicon dioxide layer, and the first conductive layer;
• forming a first dielectric spacer on the first sidewall and a second dielectric spacer on the second sidewall, where an upper surface of each sidewall is above an upper surface of the first and second spacers;
• forming a second conductive layer over the first silicon dioxide layer and over the first conductive layer;
• removing the second conductive layer from over the first conductive layer and leaving the second conductive layer at other locations;
• etching the second silicon dioxide layer, the silicon nitride layer, the first silicon dioxide layer to expose the first conductive layer;
• then
• forming a silicide layer simultaneously on the first and second conductive layers.

A method for forming a semiconductor device, comprising:

• forming a first conductive layer and at least one dielectric layer on the first conductive layer;
• forming a patterned mask layer over the at least one dielectric layer and overlying the first conductive layer;
• etching the at least one dielectric layer and the first conductive layer using the mask as a pattern to form first and second cross-sectional sidewalls from the at least one dielectric layer and the first conductive layer;
• forming a first dielectric spacer on the first sidewall and a second dielectric spacer on the second sidewall, where an upper surface of each sidewall is above an upper surface of the first and second spacers;
• forming a second conductive layer over the at least one dielectric layer and over the first conductive layer;
• removing the second conductive layer from over an entire width of the first conductive layer and leaving the second conductive layer at other locations;
• etching the at least one dielectric layer to expose the entire width of the first conductive layer;
• then
• forming a silicide layer simultaneously on the entire width of the first conductive layer and over the second conductive layer.