Process integration of SOI FETs with active layer spacer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
A method of manufacturing a microelectronics device including providing a substrate having an active layer, a dielectric layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural layer. The method further includes forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls. A spacer is formed covering a first portion of the exposed dielectric layer surface and substantially spanning one of the active layer sidewalls. At least a second portion of the exposed dielectric layer surface is then cleaned.
Claims22
A method of manufacturing a microelectronic device, comprising:
- providing a substrate having an active layer, a dielectic layer and a structural layer, wherein the active layer is formed over the dielectric layer and the dielectric layer is formed over the structural layer;
- forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls;
- cleaning the exposed surface of the dielectric layer, wherein the cleaning includes plasma cleaning employing an etch chemistry containing at least one of fluorine and a fluorine-containing gas, and then forming a spacer covering a portion of the cleaned, exposed dielectric layer surface and substantially spanning one of the active layer sidewalls;
- and
- forming a gate electrode over the active layer.
A method of manufacturing a microelectronic device, comprising:
- providing a substrate having:
- a structural layer;
- a dielectric layer located on the structural layer;
- and
- an active layer located on the dielectric layer;
- forming an opening through the active layer thereby exposing a surface of the dielectric layer and defining active layer sidewalls;
- cleaning the exposed surface of the dielectric layer, wherein the cleaning includes plasma cleaning employing an etch chemistry containing at least one of fluorine and a fluorine-containing gas, and then forming a spacer covering at least a portion of the cleaned, exposed dielectric layer surface and spanning at least a portion of the active layer sidewalls;
- and
- forming a gate electrode on the active layer.
Dependencies are inferred from the claim text.