Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratios
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsAn-Chun Tu, Jenn-Ming Huang
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Abstract
A novel sequence of process steps is provided for forming void-free interlevel dielectric layers between closely spaced gate electrodes. Closely spaced gate electrodes having sidewall spacers are formed on a substrate. After using the sidewall spacers to form self-aligned source/drain contacts and self-aligned silicide contacts, the sidewall spacers are removed. By removing the sidewall spacers, the aspect ratio of the gap between adjacent closely spaced gate electrodes is substantially reduced (from greater than 5 to less than 2), thereby preventing voids during the subsequent deposition of an ILD layer.
Claims28
A method for forming an interlevel dielectric layer with improved gap filling comprising the sequential steps of:
- providing a semiconductor substrate having closely spaced gate electrodes, with said closely spaced gate electrodes defining gaps therebetween;
- forming lightly doped source and drain regions adjacent to said gate electrodes;
- forming sidewall spacers on said gate electrodes;
- forming source/drain contact areas adjacent to said sidewall spacers;
- forming a metal silicide layer on said gate electrodes and on said source/drain contact areas;
- removing said sidewall spacers;
- and
- forming said interlevel dielectric layer over and between said gate electrodes and filling said gaps between said gate electrodes on said substrate, wherein said removal of the sidewall spacers increases the gaps between the gate electrodes.
A method for forming an interlevel dielectric layer with improved gap filling comprising the sequential steps of:
- providing a semiconductor substrate having closely spaced polysilicon gate electrodes, with said closely spaced gate electrodes defining gaps therebetween;
- forming lightly doped source and drain regions adjacent to said polysilicon gate electrodes;
- forming sidewall spacers on said polysilicon gate electrodes;
- forming source/drain contact areas adjacent to said sidewall spacers;
- forming a self-aligned metal silicide layer on said polysilicon gate electrodes and on said source/drain contact areas;
- partially removing said sidewall spacers;
- and
- forming said interlevel dielectric layer over and between said polysilicon gate electrodes and filling said gaps between said polysilicon gate electrodes on said substrate, wherein said removal of the sidewall spacers increases the gaps between the gate electrodes.
Dependencies are inferred from the claim text.