US 7,119,010 B2 · Integrated circuit with self-aligned line and via and manufacturing method therefor

Abstract

An integrated circuit and manufacturing method therefor is provided having a base with a first dielectric layer formed thereon. A second dielectric layer is formed over the first dielectric layer. A third dielectric layer is formed in spaced-apart strips over the second dielectric layer. A first trench opening is formed through the first and second dielectric layers between the spaced-apart strips of the third dielectric layer. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer between the spaced-apart strips of the third dielectric layer. Conductor metals in the trench openings form self-aligned trench interconnects.

Claims9

Dependent claims

A method used in manufacturing an integrated circuit comprising:

providing a base;
depositing a first dielectric layer over the base;
depositing a second dielectric layer over the first dielectric layer;
depositing a third dielectric layer over the second dielectric layer;
processing the third dielectric layer to open a first trench portion of the second dielectric layer;
depositing a photoresist over the second and third dielectric layers;
processing the photoresist to open a second trench portion of the first trench portion of the second dielectric layer;
removing the first and second dielectric layers under the second trench portion to form a first trench opening;
removing the photoresist;
removing the second dielectric layer under the first trench portion to form a second trench opening;
and
depositing conductor in the first and second trench openings to form a first and second trench interconnect.

9 more elements

A method used in manufacturing an integrated circuit comprising:

providing a base;
depositing a first dielectric layer over the base;
depositing a first stop layer over the first dielectric layer;
depositing a second dielectric layer over the first stop layer;
depositing a second stop layer over the second dielectric layer;
processing the second stop layer to open a first trench portion of the second dielectric layer;
depositing a photoresist over the second dielectric layer and second stop layers;
processing the photoresist to expose a second trench portion of the first trench portion of the second dielectric layer;
removing the first and second dielectric layers and the first stop layer under the second trench portion to form a first trench opening;
removing the photoresist;
removing the second dielectric layer under the first trench portion to form a second trench opening;
and
depositing conductor in the first and second trench openings to form a first and second trench, self-aligned interconnect.

10 more elements

Dependencies are inferred from the claim text.

Integrated circuit with self-aligned line and via and manufacturing method therefor

Life of this patent

Integrated circuit with self-aligned line and via and manufacturing method therefor

Life of this patent

Abstract

Claims9