Semiconductor device with dual damascene wiring

A method of manufacturing a semiconductor device, comprising:

• a step of forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie;
• a step of forming an interlayer insulating film on the insulating etch stopper film, the interlayer insulating film including a first kind of an insulating layer and a second kind of an insulating layer formed under the first kind of the insulating layer, the second kind of the insulating layer having etching characteristics different from the first kind of the insulating layer;
• a first etching step of forming a first contact hole extending from a surface of the interlayer insulating film to the second kind of the insulating layer through the first kind of the insulating layer by etching;
• a second etching step of forming a wiring trench in the first kind of the insulating layer of the interlayer insulating film and removing a remaining interlayer insulating film under the first contact hole by etching, the wiring trench having a first depth from a surface of the interlayer insulating film to an intermediate depth of the first kind of the insulating layer, and overlapping or including the first contact hole as viewed in plan;
• a step of removing the insulating etch stopper film exposed in the first contact hole to form a second contact hole continuous with the first contact hole and reaching the underlie having the conductive region;
• and
• a step of forming a dual damascene wiring layer embedded in the wiring trench and in the first and second contact holes.

A method of manufacturing a semiconductor device, comprising:

• a step of forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie;
• a step of forming an interlayer insulating film on the insulating etch stopper film, the interlayer insulating film including first, second and third kinds of insulating layers formed in this order from a bottom, the second kind of the insulating layer having etching characteristics different from the first and third kinds of the insulating layers;
• a first etching step of forming a contact hole extending from a surface of the interlayer insulating film to the insulating etch stopper film through the third, second and first kinds of the insulating layers by etching;
• a step of disposing an organic protective filler in the contact hole, the filler being higher than a surface of the first kind of the insulating layer and lower than a surface of the second kind of the insulating layer;
• a second etching step of forming a wiring trench in the third kind of the insulating layer of the interlayer insulating film by etching, the wiring trench having a first depth from a surface of the interlayer insulating film to an intermediate depth of the third kind of the insulating layer, and overlapping or including the contact hole as viewed in plan;
• a step of removing the protective filler to expose the insulating etch stopper film in the contact hole;
• a third etching step of etching the exposed etch stopper film;
• and
• a step of forming a dual damascene wiring layer embedded in the wiring trench and in the contact hole.

A method of manufacturing a semiconductor device, comprising:

• a step of forming an insulating etch stopper film on an underlie having a conductive region in a surface layer of the underlie;
• a step of forming an interlayer insulating film on the insulating etch stopper film, the interlayer insulating film including first, second and third kinds of insulating layers formed in this order from a bottom, the second kind of the insulating layer having etching characteristics different from the first and third kinds of the insulating layers;
• a first etching step of forming a contact hole extending from a surface of the interlayer insulating film to the second kind of the insulating layer through the third kind of the insulating layer by etching;
• a second etching step of etching the second kind of the insulating layer exposed at a bottom of the contact hole;
• a third etching step of forming a wiring trench in the third kind of the insulating layer of the interlayer insulating film and simultaneously etching the first kind of the insulating layer under the contact hole to expose the etch stopper film, the wiring trench having a first depth from a surface of the interlayer insulating film to an intermediate depth of the third kind of the insulating layer, and overlapping or including the contact hole as viewed in plan;
• a fourth etching step of etching the exposed etch stopper film;
• and
• a step of forming a dual damascene wiring layer embedded in the wiring trench and the contact hole.