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AssigneeChartered Semiconductor Manufacturing Ltd.
InventorsPradeep Ramachandramurthy Yelehanka, Tong Qing Chen, Zhi Yong Han, Jia Zhen Zheng, Kelvin Ong, Tian Hao Gu, Syn Kean Cheah
Estimating the term…
An integrated circuit is provided. A gate dielectric and a gate are provided respectively on and over a semiconductor substrate. A junction is formed adjacent the gate dielectric and a shaped spacer is formed around the gate. A spacer is formed under the shaped spacer and a liner is formed under the spacer. A first dielectric layer is formed over the semiconductor substrate, the shaped spacer, the spacer, the liner, and the gate. A second dielectric layer is formed over the first dielectric layer. A local interconnect opening is formed in the second dielectric layer down to the first dielectric layer. The local interconnect opening in the first dielectric layer is opened to expose the junction in the semiconductor substrate and the first gate. The local interconnect openings in the first and second dielectric layers are filled with a conductive material.
An integrated circuit comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
The components including insulated gates, e.g. IGFETs: manufacturing their gate sidewall spacers
The components including insulated gates, e.g. IGFETs: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
Term ended 7 Feb 2023 (estimated)
1. Technical Field
The present invention relates generally to integrated circuits, and more specifically to local interconnects and isolated contacts for interconnecting semiconductor devices.
2. Background Art
FIG. 1 is a view of an integrated circuit in an intermediate stage of manufacture in accordance with the present invention;
FIG. 2 is the structure of FIG. 1 after further processing;
FIG. 3 is the structure of FIG. 2 after further etching;
Referring now to FIG. 1, therein is shown an integrated circuit 100 in an intermediate stage of manufacture. The integrated circuit 100 includes a semiconductor substrate 102 having first and second gate dielectrics 104 and 106 formed on the surface of the semiconductor substrate 102 under first and second semiconductor gates 108 and 110, respectively.
The term “horizontal” as used in herein is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “side” (as in “sidewall”), “higher”, “lower”, “over”, and “under”, are defined with respect to the horizontal plane. The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure.
The first and second semiconductor gates 108 and 110 have been used to implant lightly doped source/drain junctions 112 in the semiconductor substrate 102. The lightly doped source/drain junctions 112 of different semiconductor devices, such as the first and second semiconductor devices 114 and 116, are separated by shallow trench isolations, such as a shallow trench isolation 120.