Semiconductor chip packages and methods for fabricating the same
AssigneeDongbu Electronics Co., Ltd.
InventorByoung Young Kang
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Abstract
Semiconductor chip packages of a wafer level and method for fabricating the same are disclosed, in which a wafer electrode pad is connected with an external circuit by a via-electrode penetrating a silicon wafer. An illustrated example package includes a wafer having a first surface and a second surface opposite the first surface; a semiconductor device having at least one of electrode pad on the first surface; a protective layer covering the first surface of the silicon wafer; a via-hole from the second surface to the electrode pad on the first surface, a via electrode within the via-hole; and a solder ball or a solder bump on the second surface for electrical connection between the via-electrode and an external circuit.
Claims12
A method for fabricating a semiconductor chip package comprising:
- preparing a silicon wafer having a first surface and a second surface opposite the first surface;
- forming a semiconductor device having at least one electrode pad on the first surface of the silicon wafer;
- forming a via-hole from the second surface to the electrode pad on the first surface;
- forming a via-electrode within the via-hole;
- forming a protective layer covering the first surface;
- polishing the second surface to reduce a thickness of the silicon wafer;
- and
- forming a solder bump or a solder ball on the second surface for electrical connection between the via-electrode and an external circuit.
Dependencies are inferred from the claim text.