Methods of fabricating silicon carbide devices with hybrid well regions
AssigneeCree, Inc.
InventorsMrinal Kanti Das, Sei-Hyung Ryu
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Abstract
MOS channel devices and methods of fabricating such devices having a hybrid channel are provided. Exemplary devices include vertical power MOSFETs that include a hybrid well region of silicon carbide and methods of fabricating such devices are provided. The hybrid well region may include an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer, an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends to a surface of the p-type epitaxial layer and/or an epitaxial p-type silicon carbide portion, at least a portion of the epitaxial p-type silicon carbide well portion corresponding to a p-type channel region of the MOSFET.
Claims31
A method of fabricating a silicon carbide MOSFET, comprising:
- forming a hybrid p-type silicon carbide well region on a silicon carbide substrate having a drift region, the hybrid p-type silicon carbide well region comprising:
- an implanted p-type silicon carbide well portion in a p-type silicon carbide epitaxial layer;
- an implanted p-type silicon carbide contact portion that contacts the implanted p-type silicon carbide well portion and extends to a surface of the p-type epitaxial layer;
- and
- an epitaxial p-type silicon carbide portion, at least a portion of the epitaxial p-type silicon carbide portion corresponding to a p-type channel region of the MOSFET;
- forming a first n-type silicon carbide region at least in part within the hybrid p-type silicon carbide well region;
- forming a second n-type silicon carbide region adjacent the p-type channel region and extending to the drift region to provide an n-type channel region;
- forming a gate dielectric on the second n-type silicon carbide and at least a portion of the first n-type silicon carbide region;
- forming a gate contact on the gate dielectric;
- forming a first contact so as to contact a portion of the contact portion of the hybrid p-type silicon carbide well region the first n-type silicon carbide region;
- and
- forming a second contact on the substrate.
A method of fabricating a silicon carbide power device, comprising:
- forming a first p-type silicon carbide epitaxial layer on an n-type silicon carbide drift region on an n-type silicon carbide substrate;
- forming at least one first region of n-type silicon carbide through the first p-type silicon carbide epitaxial layer and extending to the n-type silicon carbide drift region so as to provide at least one channel region in the first p-type silicon carbide epitaxial layer;
- forming at least one second region of n-type silicon carbide in the first p-type silicon carbide epitaxial layer which is adjacent and spaced apart from the first region of n-type silicon carbide;
- implanting p-type dopants in the p-type silicon carbide epitaxial layer to form at least one buried region of p-type silicon carbide in the first p-type silicon carbide epitaxial layer, the at least one buried region having a higher carrier concentration than the p-type silicon carbide epitaxial layer and being positioned between the at least one second region of n-type silicon carbide and the drift region and being substantially aligned with a side of the at least one second region of n-type silicon carbide adjacent the at least one first region of n-type silicon carbide;
- implanting p-type dopants in the p-type silicon carbide epitaxial layer to form at least one contact region of p-type silicon carbide that extends through the at least one second region of n-type silicon carbide to the at least one buried region of p-type silicon carbide;
- and
- forming a gate dielectric on the first region of n-type silicon carbide and at least a portion of the second region of n-type silicon carbide.
A method of fabricating a silicon carbide Metal-Oxide Semiconductor (MOS) gated device, comprising:
- forming a hybrid silicon carbide well region of a first conductivity type, comprising:
- forming a first silicon carbide epitaxial layer of a first conductivity type;
- implanting a ions in the silicon carbide epitaxial layer to provide an implanted well portion of the first conductivity type in the silicon carbide epitaxial layer;
- and
- implanting ions in the silicon carbide epitaxial layer to provide an implanted contact portion that contacts the implanted well portion and extends to a surface of the epitaxial layer;
- forming a first silicon carbide region of a second conductivity type at least in part within the hybrid silicon carbide well region;
- forming a second silicon carbide region of the second conductivity type adjacent the well region and spaced apart from the first silicon carbide region;
- forming a gate dielectric on the second silicon carbide region and at least a portion of the first silicon carbide region;
- forming a gate contact on the gate dielectric;
- and
- where an unimplanted portion of the epitaxial layer corresponds to a channel region of the device.
Dependencies are inferred from the claim text.