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US 7,118,949 B2Granted
Semiconductor integrated circuit device and method for manufacturing the same
AssigneeRenesas Technology Corp.
InventorsTakafumi Tokunaga, Makoto Yoshida, Fumio Ootsuka
Life of this patent
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Abstract
In a semiconductor integrated circuit device having a system-on-chip structure in which a DRAM and a logic integrated circuit are mixedly mounted on a chip, a silicide layer is formed on the surfaces of the source and the drain of a MISFET of a direct peripheral circuit of the DRAM, the surfaces of the source and the drain of a MISFET of an indirect peripheral circuit of the DRAM, and the surfaces of the source and the drain of a MISFET of the logic integrated circuit, and the silicide layer is not formed on the surfaces of the source and the drain of a memory cell selective MISFET of the memory cell of the DRAM.
Claims13
A method of manufacturing a semiconductor integrated circuit device having first MISFETs and second MISFETs formed over a semiconductor substrate, comprising the steps of
- (a) providing the semiconductor substrate including a first area and a second area;
- (b) forming a first gate electrode of the first MISFET in the first area and a second gate electrode of the second MISFET in the second area;
- (c) forming a first semiconductor region and a second semiconductor region of the first MISFET in the first area;
- (d) forming a third semiconductor region and a fourth semiconductor region of the second MISFET in the second area;
- (e) forming a first insulating film over the first gate electrode, the first and second semiconductor regions, the second gate electrode, and the third and fourth semiconductor regions;
- (f) removing the first insulating film over the third and fourth semiconductor regions in the second area, leaving the first insulating film in the first area;
- (g) after the step (f), forming a metal film over the first insulating film in the first area and on the third and fourth semiconductor regions in the second area;
- (h) performing a thermal treatment to form silicide films of the metal film on the third and fourth semiconductor regions, and not on the first and second semiconductor regions;
- (i) after the step (h), removing a part of the metal film which is not silicided in the step (h);
- (j) after the step (i), forming an interlayer insulating film over the first area and the second area;
- (k) polishing the surface of the interlayer insulating film;
- (l) etching the interlayer insulating film to form a first contact hole and a second contact hole in a self-alignment manner with the adjacent first gate electrodes in the first area;
- and
- (m) forming a first conductive film and a second conductive film in the first contact hole and the second contact hole respectively, electrically connected to the first and second semiconductor regions respectively.
11 more elements
A method of manufacturing a semiconductor integrated circuit device having a memory cell area of a DRAM and a logic circuit area, comprising the steps of
- (a) providing a semiconductor substrate comprised of silicon;
- (b) forming a word line of a memory cell selecting transistor and a gate electrode of a logic circuit MISFET in the memory cell area and the logic circuit area respectively;
- (c) forming first source and a drain regions of the memory cell selecting transistor in the memory cell area;
- (d) forming second source and a drain regions of a logic circuit MISFET in the logic circuit area;
- (e) forming a first insulating film over the word line, the first source and drain regions, the gate electrode, and the second source and drain regions;
- (f) removing the first insulating film over the second source and drain regions, leaving the first insulating film in the memory cell area;
- (g) after the step (f), forming a metal film over the first insulating film in the memory cell area and on the second source and drain regions;
- (h) performing a thermal treatment to form silicide films of the metal film on the second source and drain regions;
- (i) after the step (h), removing a part of the metal film which is not silicided in the step (h);
- (j) after the step (i), forming an interlayer insulating film over the memory cell area and the logic circuit area;
- (k) polishing the surface of the interlayer insulating film;
- (l) etching the interlayer insulating film to form a first contact hole and a second contact hole in a self alignment manner with the adjacent word lines in the memory cell area;
- (m) forming a first conductive film and a second conductive film in the first contact hole and the second contact hole respectively, wherein the first conductive film is electrically connected to one of the first source and drain regions;
- and
- the second conductive film is electrically connected to the other of the first source and drain regions;
- (n) etching the interlayer insulating film to form a third contact hole and a fourth contact hole in the logic circuit area;
- (o) forming a third conductive film and a fourth conductive film in the third contact hole and the fourth contact hole respectively, wherein the third conductive film is electrically connected to one of the second source and drain regions;
- and
- the fourth conductive film is electrically connected to the other of the second source and drain regions;
- (p) forming a bit line of the DRAM over the interlayer insulating film in the memory cell area, electrically connected to the first conductive film;
- and
- (q) forming a capacitor element of the DRAM over the interlayer insulating film in the memory cell area, electrically connected to the second conductive film;
- wherein
- after the step (f), a cap insulating film and a sidewall of the word line, made of the first insulating film, are formed;
- in the step (l), an etching rate of the interlayer insulating film is greater than an etching rate of the cap insulating film and the sidewall of the word line;
- and
- the first insulating film prevents the metal film from contacting the first source and drain regions.
24 more elements
Dependencies are inferred from the claim text.