Placement of a clock signal supply network during design of integrated circuits

#The present invention may relate to a method, apparatus and/or design tool for placing a clock signal supply network during the design of an integrated circuit. The invention may especially relate to an automated technique for placing such a network.

#One of the steps of designing an integrated circuit layout is to arrange for clock signals to be supplied to clocked cells of the circuit. A computer based design tool is used to automatically design a clock signal supply network (clock tree) according to predetermined design rules. The clock tree has multiple branches to deliver clock signals to different circuit cells, at different locations, on an integrated circuit die. The branches typically include active circuit cells through which the clock signal passes. Typical active cells include repeater cells for preserving the clock signal in long signal paths, and clock gate cells for selectively blocking or applying the clock signal. In a balanced clock tree, the branches are designed to have generally the same signal path length in each branch in an attempt to reduce clock skew between the branches.

#Controlling clock skew is an important part of the design process. Clock skew affects the relative timing at which different cells in the integrated circuit operate. Clock skew can be a limiting factor on the maximum operating speed of one or more parts of the integrated circuit or the integrated circuit as a whole. In practice, undesirable clock skew between two or more branches of a clock tree remains a significant design problem. The problem is becoming increasingly apparent as greater demands are made on speed, performance, complexity and fabrication size and density of integrated circuits. Current automatic design tools for placing clock trees lack sufficient refinement for optimizing clock trees in demanding or speed critical designs.

#Non-limiting preferred embodiments of the invention are now described, by way of example only, with reference to the claims and the accompanying drawings, in which:

#FIG. 1 is a flow diagram showing steps for placing a clock signal supply network using a design tool of a preferred embodiment of the invention;

#FIG. 2 is a schematic circuit diagram illustrating parts of a design of a first integrated circuit for which a clock signal supply network is to be prepared;

#FIG. 1 may illustrate execution steps used in a design tool (e.g., clock placement tool) 14 of a preferred embodiment of the invention. The design tool 14 may be configured to design a clock signal supply network (e.g., a clock tree) for a first circuit layout (e.g., circuit 10 in FIG. 2) for an integrated circuit 12. The design tool 14 may be computer-based. The steps may be executed on and/or by a computer. The design tool 14 may be configured to provide a balanced and/or optimized clock tree for demanding and/or speed critical circuits. The design tool 14 may take account of one or more of process, voltage and temperature (PVT) characteristics. The design tool 14 may route the clock signals to certain cells, so as to protect a relative timing of the clock signals from PVT characteristics. PVT characteristics may affect the speed and/or timing of circuitry at different locations within an integrated circuit 12. PVT characteristics may affect the speed at which circuit elements (e.g., active circuit elements) may operate. For example, PVT characteristics may affect the operating speed of repeater cells (78 described later) used in a clock tree. PVT characteristics may introduce clock skew when the PVT characteristics may be different in different branches of the clock tree and/or when the PVT characteristics affect different branches of the clock tree differently. The manner in which PVT characteristics may affect different branches of a clock tree may be difficult to control and/or predict.

#Process characteristics may include minor processing variations that may occur during fabrication of the integrated circuit 12. Minor processing variations may occur between different integrated circuits 12, or at different locations within an integrated circuit 12. Minor processing variations may, for example, include a doping level or gradient. Voltage characteristics may include voltage drops occurring while the integrated circuit 12 is in use, or an allowable voltage range over which the integrated circuit 12 may be specified for use. Temperature characteristics may include an allowable operating temperature range for the integrated circuit as a whole, or hot-spots generated at localized areas of the integrated circuit, creating a temperature gradient. The voltage and/or the temperature characteristics may vary dynamically when the integrated circuit is in use.

#The design tool 14 may be configured to place a clock tree to reduce a vulnerability to PVT induced clock skew for at least certain cells. The design tool 14 may take into account the connectivity and/or timing paths of cells. The design tool 14 may design a clock tree such that cells having a closely dependent timing are supplied with a clock signal from the same portion (e.g., branch) of the clock tree as one another.