Method of optimizing placement and routing of edge logic in padring layout design

A method of generating a padring layout design for a chip design, comprising:

• (a) defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design;
• (b) defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas, each slot describing placement of at least one of a pad metal, an I/O cell, and a standard cell within the one or more areas;
• (c) using each pattern in an instantiation process to create said slots in a respective zone, wherein said instantiation process associates each area of each slot with a particular location in said respective zone;
• (d) customizing said padring layout design;
• (e) placing edge logic in selective areas of said slots, wherein said edge logic represents one or more standard cells which are associated with an I/O cell;
• and
• (f) performing said step e) using one of a plurality of placement algorithms based on a timing constraint associated with said chip design.

A computer system comprising:

• a processor;
• and
• a memory device coupled to said processor, wherein said memory device comprises computer-executable instructions stored therein for performing a method of generating a padring layout design for a chip design, comprising:
• (a) defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design;
• (b) defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas, each slot describing placement of at least one of a pad metal, an I/O cell, and a standard cell within the one or more areas;
• (c) using each pattern in an instantiation process to create said slots in a respective zone, wherein said instantiation process associates each area of each slot with a particular location in said respective zone;
• (d) placing edge logic in selective areas of said slots, wherein said edge logic represents one or more standard cells which are associated with an I/O cell;
• and
• (e) performing said step d) using one of a plurality of placement algorithms based on a timing constraint associated with said chip design.

A computer system comprising:

• a processor;
• and
• a memory device coupled to said processor, wherein said memory device comprises computer-executable instructions stored therein for performing a method of generating a padring layout design for a chip design, comprising:
• (a) defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design;
• (b) defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas, each slot describing placement of at least one of a pad metal, an I/O cell, and a standard cell within the one or more areas;
• (c) using each pattern in an instantiation process to create said slots in a respective zone, wherein said instantiation process associates each area of each slot with a particular location in said respective zone;
• (d) customizing said padring layout design;
• (e) placing edge logic in selective areas of said slots, wherein said edge logic represents one or more standard cells which are associated with an I/O cell;
• and
• (f) performing said step e) using one of a plurality of placement algorithms based on a timing constraint associated with said chip design.

A method of generating a padring layout design for a chip design, comprising:

• defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design;
• defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas, one of said areas comprises an edge logic area for placing said edge logic, said edge logic area overlaps a core region of said chip design;
• using each pattern in an instantiation process to create said slots in a respective zone, wherein said instantiation process associates each area of each slot with a particular location in said respective zone;
• placing edge logic in selective areas of said slots, wherein said edge logic represents one or more standard cells which are associated with an I/O cell;
• and
• performing said placing using one of a plurality of placement algorithms based on a timing constraint associated with said chip design.

A method of generating a padring layout design for a chip design, comprising:

• defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design;
• defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas, one of said areas comprises an edge logic area for placing said edge logic, said edge logic area overlaps a core region of said chip design;
• using each pattern in an instantiation process to create said slots in a respective zone, wherein said instantiation process associates each area of each slot with a particular location in said respective zone;
• customizing said padring layout design;
• placing edge logic in selective areas of said slots, wherein said edge logic represents one or more standard cells which are associated with an I/O cell;
• and
• performing said placing using one of a plurality of placement algorithms based on a timing constraint associated with said chip design.

A computer system comprising:

• a processor;
• and
• a memory device coupled to said processor, wherein said memory device comprises computer-executable instructions stored therein for performing a method of generating a padring layout design for a chip design, comprising:
• defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design;
• defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas;
• using each pattern in an instantiation process to create said slots in a respective zone, wherein said instantiation process associates each area of each slot with a particular location in said respective zone, wherein one of said areas comprises an edge logic area for placing said edge logic, edge logic area overlaps a core region of said chip design;
• placing edge logic in selective areas of said slots, wherein said edge logic represents one or more standard cells which are associated with an I/O cell;
• and
• performing said placing using one of a plurality of placement algorithms based on a timing constraint associated with said chip design.

A computer system comprising:

• a processor;
• and
• a memory device coupled to said processor, wherein said memory device comprises computer-executable instructions stored therein for performing a method of generating a padring layout design for a chip design, comprising:
• defining one or more styles for said padring layout design, each style comprising one or more zones each representing a portion of said padring layout design;
• defining one or more patterns for said one or more zones, wherein each pattern represents a template for one or more slots each comprising one or more areas, one of said areas comprises an edge logic area for placing said edge logic, said edge logic area overlaps a core region of said chip design;
• using each pattern in an instantiation process to create said slots in a respective zone, wherein said instantiation process associates each area of each slot with a particular location in said respective zone;
• customizing said padring layout design;
• placing edge logic in selective areas of said slots, wherein said edge logic represents one or more standard cells which are associated with an I/O cell;
• and
• performing said placing using one of a plurality of placement algorithms based on a timing constraint associated with said chip design.