Methods for optimizing package and silicon co-design of integrated circuit
AssigneeLSI Logic Corporation
InventorsAnwar Ali, Stan Mihelcic, James G. Monthie
Life of this patent
Estimating the term…
Abstract
The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.
Claims32
A method for optimizing package and silicon co-design of an integrated circuit, comprising steps of:
- creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit;
- reviewing PCB and Die constraints of said integrated circuit;
- generating, based on a second library including at least one partial package template, a partial package design for said integrated circuit;
- starting a partial silicon design for said integrated circuit;
- completing a full package design for said integrated circuit;
- and
- completing a full silicon design for said integrated circuit.
A computer-readable medium having computer-executable instructions for performing a method for optimizing package and silicon co-design of an integrated circuit, said method comprising:
- creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit;
- reviewing PCB and Die constraints of said integrated circuit;
- generating, based on a second library including at least one partial package template, a partial package design for said integrated circuit;
- starting a partial silicon design for said integrated circuit;
- completing a full package design for said integrated circuit;
- and
- completing a full silicon design for said integrated circuit.
A method for optimizing package and silicon co-design of an integrated circuit, comprising steps of:
- creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit;
- reviewing PCB and Die constraints of said integrated circuit;
- generating, based on a second library including at least one partial package template, a full package design for said integrated circuit;
- and
- completing a full silicon design for said integrated circuit.
A computer-readable medium having computer-executable instructions for performing a method for optimizing package and silicon co-design of an integrated circuit, said method comprising:
- creating, based on a first library including at least one bump pattern template, a composite bump pattern for an integrated circuit;
- reviewing PCB and Die constraints of said integrated circuit;
- generating, based on a second library including at least one partial package template, a full package design for said integrated circuit;
- and
- completing a full silicon design for said integrated circuit.
Dependencies are inferred from the claim text.