Identifying specific netlist gates for use in code coverage testing

A computer readable storage medium having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for identifying gates of specified functionality in an ASIC design, the method comprising;

• limiting a search of a source file to gates with output which meets an intended criteria,
• creating and applying design elements to a smaller netlist in a synthesis tool to add one exclusive-nor gate (XNOR) into the smaller netlist for each an output signal which meets said intended criteria in the target signal set, and tying one input of said one XNOR to said output signal,
• tying an other input of said one XNOR to a new input added to the ASIC design wherein there is one such new input for entire design, and all said one XNORs are tied to this one such new input,
• tying the output of each one XNOR to a new XNOR output signal created in the design, wherein there is one said new XNOR output signal for each XNOR,
• identifying the new XNOR signals by common prefix and a unique number for each XNOR,
• creating a VHDL netlist from said smaller netlist with additional features added by program means for creating said design features and tying their signals into said smaller netlist,
• analyzing said new XNOR output signals from all said one XNORs to determine which of the said new one XNOR gates have said specified function after running an event-based simulator repeatedly until all entries on a truth table for a specified function are filled, and
• producing a file indicating how many gates have the specified function.

A method for identifying netlist gates with specified functionality in a circuit design for use by a code coverage tool, said method comprising:

• limiting a search to gates with an output signal which meets an intended criteria by specifying a truth table for the output signal and input signals as said intended criteria for said gates,
• creating and adding an instrument design element to a smaller netlist in a synthesis tool such that one instrument gate is added into the smaller netlist for each said output signal which meets said intended criteria in a target signal set, and tying one input of said one instrument gate to said output signal,
• tying an other input of said one instrument gate to a new input added to the circuit design wherein there is one such new input for entire design, and all said one instrument gate are tied to this one such new input,
• tying the output of each one instrument gate to a new instrument gate output signal created in the design, wherein there is one said new instrument gate output signal for each instrument gate,
• identifying the new instrument gate output signals by common prefix and a unique number for each XNOR,
• creating a netlist,
• bringing up said netlist in an event based simulator,
• running an event-based simulator repeatedly until all entries on said truth table are filled,
• analyzing said new instrument gate output signals from all said one instrument gates to determine which of said one instrumented gates have a specified function.

A computer readable storage medium having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method for identifying netlist gates with specified functionality in an ASIC design for use by a code coverage tool, said method comprising:

• limiting a search to gates with an output signal which meets an intended criteria by specifying a truth table for the output signal and input signals as said intended criteria for said gates,
• creating and adding an instrument design element to the smaller netlist in a synthesis tool wherein one instrument gate is added into the smaller netlist for each said output signal which meets said intended criteria in a target signal set, and tying one input of said one instrument gate to said output signal,
• tying an other input of said one instrument gate to a new input added to the ASIC design wherein there is one such new input for entire design, and all said one instrument gate are tied to this one such new input,
• tying the output of each one instrument gate to a new instrument gate output signal created in the ASIC design, such that there is one said new instrument gate output signal for each instrument gate,
• identifying the new instrument gate output signals by common prefix and a unique number for each XNOR,
• creating a netlist,
• bringing up said netlist in an event based simulator,
• running an event-based simulator repeatedly until all entries on said truth table are filled, and
• analyzing said new instrument gate output signals from all said one instrument gates to determine which instrumented gates have a specified function.