Current scheduling system and method for optimizing multi-threshold CMOS designs
AssigneeSequence Design, Inc.
InventorGerald L. Frenkil
Life of this patent
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Abstract
This invention provides a mechanism for minimizing the switching time degradation of MTCMOS circuits while at the same time minimizing the area overhead due to the MTCMOS switch circuitry. This optimization is achieved by scheduling the current flow, due to the switching events of the MTCMOS logic cells, such that only temporally mutually exclusive currents, or currents whose cumulative sum is less than a predetermined value, can flow in any given switch cell. Techniques for current event merging and current event culling, and techniques for handling timing and current variances may be used.
Claims54
A method for optimizing a power-gated design, comprising:
- dividing a time period into a plurality of timing windows;
- mapping current events in each element of the power-gated design to one or more of the timing windows according to whether or not a current event of the element occurs within each timing window;
- providing a plurality of switch devices, each switch device having a first terminal coupled to a physical power supply, a second terminal coupled to provide a virtual power supply, and a third terminal receiving a control signal that enables a low impedance path between the first terminal and the second terminal;
- and
- assigning each element of the power-gated design to one of these switch devices according to the mapping of current events in each element to the timing windows.
A system for optimizing a power-gated design within an integrated circuit design automation system, comprising:
- a mapping module that analyzes current events in each element of the power-gated design and maps each current event to one or more timing windows according to whether or not the current event of the element occurs within each timing window, the timing windows being non-overlapping intervals of time within a predetermined time period in the power-gated design;
- a switch device provisioning module that provides a plurality of switch devices in the power-gated device, each switch device having a first terminal coupled to a physical power supply, a second terminal coupled to provide a virtual power supply, and a third terminal receiving a control signal that enables a low impedance path between the first terminal and the second terminal;
- and
- a switch device assignment module that associates each element of the power-gated design to one of these switch devices according to the mapping of current events in each element to the timing windows.
Dependencies are inferred from the claim text.