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AssigneeInternational Business Machines Corporation
InventorsJeffrey H Oppold, Michael R Ouellette, Larry Wissell
Estimating the term…
A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a “don't care” state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.
An apparatus for identifying soft errors in memory devices having a plurality of logic registers for steering memory selection away from single bit slices or rows having defects to spare, redundant single bit slices or rows, said apparatus comprising an electrical connection of each of said registers to a corresponding exclusive OR logic device, each of said corresponding exclusive OR logic devices serially connected together as a string of logic devices, providing an exclusive OR logic device signal output to a next sequential exclusive OR logic device input based upon a comparison of preceding sequential register output and a preceding exclusive OR logic device output during a parity check, and further including having an initial exclusive OR logic device with a register output for each input.
A method of performing yield enhancement in memory devices having a plurality of logic registers for steering memory selection away from single bit slices or rows having defects to spare, redundant single bit slices or rows, said method comprising:
Dependencies are inferred from the claim text.