Decoder architecture for reed solomon codes

A method of decoding error correcting codes, comprising:

• calculating a plurality of syndromes;
• calculating a plurality of polynomials from said calculated plurality of syndromes;
• rotating at least one of said calculated plurality of polynomials if said at least one of said calculated plurality of polynomials overflows;
• calculating one coefficient of each of said polynomials in each of a plurality of clock cycles;
• performing a single multiplying step in calculating each said coefficient;
• and
• performing each said multiplying step a plurality of times in successive clock cycles to determine a plurality of coefficients of each of said polynomials.

A method of correcting errors for decoding error correcting codes, comprising:

• calculating an error evaluation polynomial comprising a plurality of coefficients;
• multiplying each of said plurality of coefficients of said error evaluation polynomial by a first factor if each said coefficient has overflowed;
• and
• multiplying each of said plurality of coefficients of said error evaluation polynomial by a second factor different from said first factor if each said coefficient has not overflowed;
• whereby said error evaluation polynomial is evaluated.

Apparatus for decoding error correcting codes, comprising:

• means for calculating a plurality of syndromes;
• means for calculating a plurality of polynomials from said calculated plurality of syndromes;
• means for rotating at least one of said calculated plurality of polynomials if said at least one of said calculated plurality of polynomials overflows;
• means for calculating one coefficient of each of said polynomials in each of a plurality of clock cycles;
• means for performing a single multiplying step in calculating each said coefficient;
• and
• means for performing each said multiplying step a plurality of times in successive clock cycles to determine a plurality of coefficients of each of said polynomials.