US 7,117,421 B1 · Transparent error correction code memory system and method

Abstract

The present invention provides flexible and efficient memory configuration that is capable of economically addressing both resource consumption and ECC concerns. A memory system facilitates transparent ECC operations without dedicated ECC connections. A first dynamic random access memory structure stores data, wherein the data connections to the memory system are limited to the width of the first dynamic random access memory structure. A second dynamic random access memory structure dedicated to storing error correction code information, wherein the error correction code information is accessed via the data connections. In one exemplary implementation, the first memory structure and the second memory structure the data and ECC are included in the same memory bank. In an alternate implementation, the first memory structure and the second memory structure the data and ECC are included in the different memory banks and are accessed in parallel.

Claims34

Dependent claims

A memory system comprising:

a first random access memory structure for storing data, wherein data connections to said memory system are limited to the data width of said first random access memory structure, the data width not including error correction code information;
and
a second random access memory structure dedicated to storing error correction code information, wherein said error correction code information is accessed via said data connections.

Dependencies are inferred from the claim text.

Transparent error correction code memory system and method

Life of this patent

Transparent error correction code memory system and method

Life of this patent

Abstract

Claims34