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US 7,117,420 B1Granted
Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories
AssigneeLSI Logic Corporation
InventorsMax M. Yeung, Richard J. Stephani, Miguel A. Vilchis
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Abstract
An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a read data signal and a read parity signal. The second circuit may be configured to (i) detect an error when the bits of the syndrome signal are not all the same state and (ii) generate an error location signal in response the syndrome signal. The error location signal may be generated in response to fewer than all of the bits of the syndrome signal.
Claims20
An apparatus for memory error control coding comprising:
- a syndrome encoder circuit configured to (i) receive a read data signal and a read parity signal and (ii) generate a first syndrome signal in response to said read data signal and said read parity signal;
- a bypass circuit configured to (i) receive said first syndrome signal and a bypass signal and (ii) generate a second syndrome signal in response to said first syndrome signal and said bypass signal, wherein said bypass circuit comprises one or more logic gates configured to (i) receive said first syndrome signal at a first input, (ii) receive said bypass signal at a second input and (iii) present said second syndrome signal at an output;
- a detector circuit configured to (i) receive said second syndrome signal, (ii) detect an error when bits of said second syndrome signal are not all the same state and (iii) generate one or more single error signals when a single bit error is detected in said read data and said read parity signals, a double error signal when an error is detected in two bits of said read data and read parity signals, and an error detected signal when either one of said one or more single error signals or said double error signal are asserted in response to said second syndrome signal;
- a locator circuit configured to (i) receive said second syndrome signal and (ii) generate an error location signal in response to said second syndrome signal, wherein said error location signal (i) is generated in response to fewer than all of said bits of said second syndrome signal and (ii) describes a location of a single bit error detected in said read data and said read parity signals;
- and
- a corrector circuit configured to (i) receive said read data signal, said read parity signal, said error location signal and said one or more single error signals and (ii) generate a corrected representation of said read data and said read parity signals in response to said error location signal when a single bit error is detected.
3 more elements
An apparatus for memory error control coding comprising:
- means for generating a first syndrome signal in response to a read data signal and a read parity signal;
- means for generating a second syndrome signal in response to said first syndrome signal and a bypass signal, wherein (i) each bit of said second syndrome signal has a state determined by a corresponding bit of said first syndrome signal when said bypass signal is in a first state and (ii) all bits of said second syndrome signal have the same state when said bypass signal is in a second state;
- means for (i) detecting an error when bits of said second syndrome signal are not all the same state and (ii) generating an error location signal, an error detected signal, a double error signal and one or more single error signals in response to said second syndrome signal, wherein said error location signal (i) is generated in response to fewer than all of said bits of said second syndrome signal and (ii) describes a location of a single bit error detected in said read data and said read parity signals;
- and
- means for generating a corrected representation of said read data and said read parity signals in response to said error location signal when a single bit error is detected.
2 more elements
A method for memory error detection and correction comprising the steps of:
- (A) generating a first syndrome signal in response to a read data signal and a read parity signal;
- (B) generating a second syndrome signal in response to said first syndrome signal and a bypass signal, wherein (i) each bit of said second syndrome signal has a state determined by a corresponding bit of said first syndrome signal when said bypass signal is in a first state and (ii) all bits of said second syndrome signal have the same state when said bypass signal is in a second state;
- (C) detecting an error when bits of said second syndrome signal are not all the same state;
- and
- (D) generating an error location signal, an error detected signal, a double error signal and one or more single error signals in response to said second syndrome signal, wherein said error location signal (i) is generated in response to fewer than all of said bits of said second syndrome signal and (ii) describes a location of a single bit error detected in said read data and said read parity signals.
2 more elements
Dependencies are inferred from the claim text.