Method for identifying an integrated circuit
AssigneeInfineon Technologies AG
InventorRalf Hartmann
Life of this patent
Estimating the term…
Abstract
An identifier is provided for an integrated circuit with a memory composed of a multiplicity of memory cells. The circuit has a manufacture-related memory cell defect pattern formed of defective memory cells. The method of identifying the integrated circuit utilizes the memory cell defect pattern to generate a circuit identification number for identifying the integrated circuit.
Claims14
A method for identifying an integrated circuit having a memory including a multiplicity of memory cells and having a manufacture-related memory cell defect pattern including defective memory cells, the integrated circuit performing a self test when switched on, the method comprising:
- acquiring addresses of defective memory cells from the self test of the integrated circuit;
- generating a circuit identification number as a function of the addresses of defective memory cells for identifying the integrated circuit;
- and
- comparing the circuit identification number with an original circuit identification number by an equipment program, the original circuit identification number being generated in a manufacturer test operation, the equipment program enabling a piece of equipment containing the integrated circuit if the circuit identification number generated in accordance with the self test is identical to the original circuit identification number.
A method for generating a circuit identification for identifying an integrated circuit having a memory including a multiplicity of memory cells and including a manufacture-related memory cell defect pattern including defective memory cells, the method comprising:
- acquiring addresses of defective memory cells from a self test on the integrated circuit;
- generating a circuit identification number as a function of the addresses of defective memory cells for identifying the integrated circuit;
- and
- permanently storing the addresses of the defective memory cells with addresses of the associated backup memory cells in an address conversion memory of the integrated circuit for address diversion, the addresses of the defective memory cells identifying the integrated circuit.
An integrated circuit identification method comprising the steps of:
- providing an integrated circuit having a memory, including a multiplicity of memory cells and a manufacture-related memory cell defect pattern including defective memory cells;
- performing a self test on the integrated circuit when switching on the integrated circuit for acquiring addresses of defective memory cells;
- and
- generating a circuit identification number as a function of the addresses of defective memory cells for identifying the integrated circuit.
Dependencies are inferred from the claim text.