Distributed failure analysis memory for automatic test equipment
AssigneeTeradyne, Inc.
InventorGrady Borders
Life of this patent
Estimating the term…
Abstract
A failure analysis memory is disclosed for use with a semiconductor tester for storing bit image failure information relating to a memory-under-test. The semiconductor tester has a plurality of channel cards disposed proximate the memory-under-test. The failure analysis memory includes a memory controller and a plurality of memory units disposed in communication with the memory controller. The memory units are distributed on the channel cards.
Claims14
A failure analysis memory system for use with a semiconductor tester for storing bit image failure information relating to a memory-under-test, the semiconductor tester having a plurality of testhead channel cards disposed in a testhead between the workstation and an interface for the memory-under-test, the failure analysis memory system including:
- a memory controller;
- and
- a plurality of reduced latency DRAM memory units disposed in communication with the memory controller and distributed on the channel cards, the memory controller controlling an internal banking of the plurality of reduced latency DRAM memory units so as to cause each of the plurality of reduced latency DRAM memory units to comprise:
- a data download portion;
- a first hidden transfer portion of catch RAM;
- a second hidden transfer portion of catch RAM;
- and
- a large vector memory portion.
Automatic test equipment for testing semiconductor devices, the automatic test equipment including:
- a host computer;
- a testhead comprising channel circuitry disposed in the testhead between a device-under-test interface and the host computer;
- and
- a failure analysis memory disposed with the channel circuitry in the testhead, the failure analysis memory comprising a plurality of reduced latency DRAM configured such that each of the plurality of reduced latency DRAM comprises:
- a data download portion;
- a first hidden transfer portion of catch RAM;
- a second hidden transfer portion of catch RAM;
- and
- a large vector memory portion.
A configurable distributed memory system for use with a semiconductor tester having a plurality of testhead channel cards disposed in a testhead between the workstation and an interface for a device-under-test, the configurable distributed memory system comprising:
- a) a memory controller;
- and
- b) a plurality of configurable memory units disposed in communication with the memory controller and distributed on the testhead channel cards, the memory controller being adapted to configure the plurality of memory units to comprise more than one of:
- (1) catch RAM;
- (2) large vector memory;
- (3) fail vector memory;
- or (4) subroutine vector memory.
Dependencies are inferred from the claim text.