Method for testing a semiconductor memory having a plurality of memory banks

A method for testing a semiconductor memory having a plurality of memory banks, the testing involving test writing of information to memory addresses, reading the information from the memory addresses and checking whether the written information has been stored correctly, which comprises the steps of:

• defining a plurality of subareas actuated independently of one another for a memory address array in each of the memory banks;
• using first commands for accessing a first subarea of the memory address array in a respective memory bank and second commands for accessing a second subarea of the memory address array in the respective memory bank to form, for each of the memory banks, a compressed command sequence associated with the respective memory bank, the first commands being associated with uneven clock periods and the second commands being associated with even clock periods;
• and
• test writing and reading the information by executing in all of the memory banks respective compressed command sequences associated with the memory banks in parallel.