Background block erase check for flash memories

A block erase check apparatus integrated with a non-volatile memory device on a semiconductor chip, comprising:

• an input-output device that communicates with an off-chip device;
• a command interface that interprets signals received by the input-output device;
• a state machine that executes a sequence of erase check operations in response to one or more signals from the command interface, wherein the state machine executes the erase check operations according to a predetermined erase check margin that is different than a predetermined erase verify margin;
• and
• a register, readable by the off-chip device, that provides status information on the erase check operations executed by the state machine.

A method for performing an erase check of a flash memory, comprising:

• sending a command to an on-chip state machine for initiating a block erase check operation;
• executing the block erase check operation on the on-chip state machine with reference to a predetermined voltage, wherein the predetermined voltage is different than a normal erase verify voltage;
• and
• signaling if an error is encountered while performing the block erase check operation.

A system comprising:

• a non-volatile memory coupled to a processor and a power supply, and a memory erase check circuit integrated on-chip with the non-volatile memory, comprising:
• an input-output device for communicating with an off-chip device;
• a command interface that interprets signals received from the input-output device;
• a state machine that executes a sequence of erase check operations in response to one or more signals from the command interface, wherein the state machine executes the sequence of erase check operations according to a predetermined erase check margin that is different than a normal erase verify margin;
• and
• a signaling device, readable by the off-chip device, that provides status information on the erase check operations executed by the state machine.

A method for checking that non-volatile memory has been erased, comprising:

• performing a normal erase operation, including an erase verify, of the non-volatile memory to a first predetermined margin;
• performing a block erase check of the non-volatile memory to a second predetermined margin subsequent to the normal erase operation, wherein the second predetermined margin is different than the first predetermined margin;
• and
• providing a signal readable by an off-chip device if an error is detected.

A system comprising:

• a non-volatile memory chip coupled to a processor and a power supply, and
• a memory erase check circuit integrated on-chip with the non-volatile memory, comprising:
• an input-output device for communicating with an off-chip device;
• a command interface that interprets signals received from the input-output device;
• control circuitry that executes a sequence of erase check operations subsequent to normal erase and erase verify operations and in response to one or more signals from the command interface, wherein the control circuitry is adapted to perform the erase check operations at a different margin than the erase verify operations;
• and
• a signaling device, readable by the off-chip device, that provides status information on the erase check operations executed by the state machine.

A block erase check apparatus integrated with a non-volatile memory device on a semiconductor chip, comprising:

• an input-output device that communicates with an off-chip device;
• a command interface that interprets signals received by the input-output device;
• a state machine that executes a sequence of erase check operations subsequent to a normal erase and erase verify, and in response to one or more signals from the command interface, wherein the state machine is adapted to perform the erase check operations at a different margin than the erase verify;
• and
• a register, readable by the off-chip device, that provides status information on the erase check operations executed by the state machine.