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US 7,117,401 B2Granted
Method and apparatus for optimizing timing for a multi-drop bus
AssigneeIntel Corporation
InventorsJoseph H. Salmon, Hing Y. To
Life of this patent
Estimating the term…
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AssigneeIntel Corporation
InventorsJoseph H. Salmon, Hing Y. To
Estimating the term…
A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.
A memory device comprising:
A memory controller comprising:
A system, comprising:
The system 11 wherein the memory device further comprises a bus interface unit to transmit the test pattern.
The system 12 wherein the memory device further comprises a mode select register to store the test mode value.
The system 11 wherein the memory controller further comprises a bus interface unit to receive the test pattern from the memory device.
A method, comprising:
Dependencies are inferred from the claim text.