Memory device with data line steering and bitline redundancy
AssigneeInternational Business Machines Corporation
InventorsKevin A. Batson, Robert E. Busch, Garrett S. Koch, Fred J. Towler, Reid A. Wistort
Life of this patent
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Abstract
An integrated circuit including: a set of bitlines; a set of data lines; means for coupling each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, the second respective bitline being adjacent to the first respective bitline; and means for maintaining the first respective bitline at a desired potential after the data line is coupled to the second bitline.
Claims26
An integrated circuit comprising:
- a set of bitlines;
- a set of data lines;
- a coupling circuit that directly connects each respective data line to a first respective bitline or to a second respective bitline based on a steering signal, said second respective bitline being adjacent to said first respective bitline;
- and
- a circuit that maintains said first respective bitline at a desired potential after said data line is coupled to said second bitline.
A method of replacing, in an integrated circuit having a multiplicity of data lines and a multiplicity of bitlines, a first bitline wit a second bitline comprising:
- providing a set of said multiplicity of said bitlines;
- providing a set of said multiplicity of said data lines;
- connecting each respective data line to a first respective bitline or to a second respective bitline through a switch and based on a steering signal supplied to said switch, said second respective bitline being adjacent to said first respective bitline;
- and
- maintaining said first respective bitline at a desired potential after said data line is coupled to said second bitline.
The method of 12 wherein all said data lines in said set of data lines are arranged in a serial order and further including:
- connecting each data line, after said data that has been connected to said second respective bitline, to corresponding respective second bitlines.
A content addressable memory comprising:
- a set of bitlines;
- a set of data lines, a number of said data lines less than a number of said bitlines;
- a set of read lines, a number of said read lines equal to said number of said data lines, each said read line coupled to one corresponding bitline of said set of bitlines;
- means for directly connecting each respective data line to a first-respective bitline or to a second respective bitline based on a steering signal, said second respective bitline being adjacent to said first respective bitline;
- means for coupling each respective read line to a first respective read line or to a second respective read line based on said steering signal, said second respective read line being adjacent to said first respective read line;
- and
- means for maintaining said first respective bitline at a known fixed state after said data line is connected to said second respective bitline.
Dependencies are inferred from the claim text.