Built-in self-test circuit
AssigneeFujitsu Limited
InventorRyuji Shimizu
Life of this patent
Estimating the term…
Abstract
A built-in self-test (BIST) circuit is configured to divide data output bits of a RAM macro into a plurality of groups each consisting of 2 bits, and provide a 1-bit comparator of a signature analyzer for each group to share one 1-bit comparator by respective two data output bits. A selector of a bit changer sequentially selects a data output bit from each group, and the 1-bit comparator sequentially compares output data for the selected data output bit with expected value data.
Claims13
A built-in self-test (BIST) circuit that is included in a large-scale integrated circuit (LSI) for testing a random-access memory (RAM) that outputs a plurality of bit sets each of which includes a plurality of bits, comprising:
- a selector that is supplied with one of the bit sets and selects the bits in the bit set one by one;
- a 1-bit comparator that compares a bit selected by the selector with expected value data;
- a data generator that supplies the expected value data to the 1-bit comparator;
- and
- a controller that controls the data generator to generate the expected value data, wherein
- a pair of the selector and the 1-bit comparator is provided to each of the bit sets.
A built-in self-test (BIST) circuit that is included in a large-scale integrated circuit (LSI) for testing a random-access memory (RAM) that outputs a plurality of bit sets, each of which includes a plurality of bits, so that the bits in each of the bit sets are output through different ports of the RAM comprising:
- a selector that is supplied with one of the bit sets and selects the bits in the bit set one by one;
- a 1-bit comparator that compares a bit selected by the selector with expected value data;
- a data generator that supplies the expected value data to the 1-bit comparator;
- and
- a controller that controls the data generator to generate the expected value data, wherein
- a pair of the selector and the 1-bit comparator is provided for each of the bit sets.
A built-in self-test (BIST) circuit that is included in a large-scale integrated circuit (LSI) for testing a random-access memory (RAM) that outputs a plurality of bit sets, each of which includes a plurality of bits, so that the bits in each of the bit sets are output through different ports of the RAM comprising:
- a first selector that is supplied with a first bit set of the bit sets and selects the bits in the first bit set one by one;
- a second selector that is supplied with a second bit set of the bit sets and selects the bits in the second bit set one by one;
- a third selector that is connected to the first selector and the second selector and selects the bits selected by the first selector and the second selector one by one;
- a 1-bit comparator that is connected to the third selector and compares a bit selected by the third selector with expected value data;
- a data generator that supplies the expected value data to the 1-bit comparator;
- and
- a controller that controls the data generator to generate the expected value data, wherein
- a set of the first selector, the second selector, the third selector, and the 1-bit comparator is provided for every predetermined number of bit sets.
Dependencies are inferred from the claim text.