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US 7,117,389 B2Granted
Multiple processor core device having shareable functional units for self-repairing capability
AssigneeInternational Business Machines Corporation
InventorDavid Arnold Luick
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Abstract
Multiple processor cores are implemented on a single integrated circuit chip, each having its own respective shareable functional units, which are preferably floating point units. A failure of a shareable unit in one processor causes that processor to share the corresponding unit in another processor on the same chip. Preferably, a functional unit is shared on a cycle interleaved basis.
Claims15
A processing device, comprising:
- a plurality of processor cores on a common integrated circuit chip, each processor core containing a respective shareable functional unit for performing operations of a first type;
- and
- control logic detecting a failure of a first of said shareable functional units in a first processor core of said plurality of processor cores, and responsive to detecting said failure, placing a second functional unit in second processor core of said plurality of processor cores in a shared mode of operation, wherein said second functional unit executes operations of said first type originating in said first processor core concurrently with executing operations of said first type originating in said second processor core.
A digital data processing system, comprising:
- a memory;
- at least one multiple-processor-core device, each said-multiple-processor core device comprising:
- (a) a plurality of processor cores on a common integrated circuit chip, each processor core executing at least one respective thread of instructions stored in said memory, each processor core containing a respective shareable functional unit for performing operations of a first type;
- and
- (b) control logic detecting a failure of a first of said shareable functional units in a first processor core of said plurality of processor cores, and responsive to detecting said failure, placing a second functional unit in a second processor core of said plurality of processor cores in a shared mode of operation, wherein said second functional unit executes operations of said first type originating in said first processor core concurrently with executing operations of said first type originating in said second processor core;
- and
- at least one communications bus transmitting data between said memory and said at least one multiple-processor-core device.
4 more elements
Dependencies are inferred from the claim text.