Timing method and apparatus for digital logic circuits
AssigneeRealtek Semiconductor Corp.
InventorsJin-Ru Chen, Chun-Feng Liu, Chang-Lien Wu
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AssigneeRealtek Semiconductor Corp.
InventorsJin-Ru Chen, Chun-Feng Liu, Chang-Lien Wu
Estimating the term…
A differentiated granularity timing apparatus and a method to provide various flexible timing granularities without requiring much memory space and complex circuit design are disclosed. The differentiated granularity timing apparatus of the present invention comprises a differentiated granularity timing unit, a comparing unit, an adder and a buffer. The buffer is for storing a time value. The comparing unit further comprises a comparator and a plurality of predetermined time interval values stored therein. The comparator is for outputting a control signal according to the time value. The differentiated granularity timing unit further comprises a multiplexer and a plurality of timers. Each timer is for providing a timing signal with different timing granularities respectively. The multiplexer is for outputting one of the timing signals with the corresponding timing granularity according to the control signal.
A timing method, comprising the following steps:
A timing apparatus, comprising:
A timing apparatus, comprising:
A timing method comprising:
Dependencies are inferred from the claim text.