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US 7,117,352 B1Granted
Debug port disable mechanism
AssigneeLSI Logic Corporation
InventorsChristopher M. Giles, Simon Bewick, Kalvin E. Williams
Life of this patent
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Abstract
A circuit generally comprising a debug port and a processor is disclosed. The processor may be configured to (i) bootstrap to a first memory, (ii) disable said debug port while in a first mode of at least three modes, (iii) authenticate said debug port while in a second mode of said modes and (iv) disable said debug port in response to failing said authentication.
Claims20
A circuit comprising:
- a debug port;
- and
- a processor configured to (i) bootstrap to a first memory while in a highest mode of security, (ii) disable said debug port while in said highest mode of security, (iii) authenticate said debug port, (iv) disable said debug port before transitioning to an intermediate mode of security in response to failing said authentication and (v) enable said debug port while in a lowest mode of said security.
A method of operating a circuit comprising the steps of:
- (A) bootstrapping to a first memory while in a highest mode of security;
- (B) disabling a debug port while in said highest mode of security;
- (C) authenticating said debug port;
- (D) disabling said debug port before transitioning to an intermediate mode of security in response to failing said authentication;
- and
- (E) enabling said debug port while in a lowest mode of said security.
3 more elements
A circuit comprising:
- means for bootstrapping to a first memory while in a highest mode of security;
- means for disabling a debug port while in said highest mode of security;
- means for authenticating said debug port;
- means for disabling said debug port before transitioning to an intermediate mode of security in response to failing said authentication;
- and
- means for enabling said debug port while in a lowest mode of said security.
3 more elements
Dependencies are inferred from the claim text.