Processor including fallback branch prediction mechanism for far jump and far call instructions

Abstract

A method and apparatus are provided for processing far jump-call branch instructions within a processor in a manner which reduces the number of stalls of the processor pipeline. The processor includes an apparatus, for providing a fallback far jump-call speculative target address that corresponds to a current far jump-call branch instruction. The microprocessor apparatus includes a far jump-call branch target buffer and a fallback speculative target address generator. The far jump-call branch target buffer stores a plurality of code segment bases and offsets corresponding to a plurality of previously executed far jump-call branch instructions, and determines if a hit for the current far jump-call branch instruction is contained therein. The fallback speculative target address generator is coupled to the far jump-call branch target buffer. In the event of a miss in the far jump-call branch target buffer, the fall back speculative target address generator generates the fallback far jump-call speculative target address from a current code segment base and a target offset, the target offset corresponding to the current far jump-call branch instruction.

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