Processor execution, pipeline sharing instruction, and data source path

A processor execution pipeline, comprising:

• a first latch circuit provided in a current processing stage for storing a first data;
• a first instruction decoding unit that determines at least a kind of instruction in the current processing stage, that decodes a first instruction into a first control signal, and that decodes all other instructions with the exception of the first instruction into a second control signal upon determining at least the kind of instruction;
• a first processing unit provided in the current processing stage and connected to the first instruction decoding unit, the first processing unit being configured to perform a first operation on a first data when receiving the first control signal;
• a bypass line provided in parallel with the first processing unit;
• a multiplexer provided in the current processing stage for selecting one of an output of the first processing unit or the first data held in the first latch circuit based on an output of the first instruction decoding unit;
• a second latch circuit provided between the current processing stage and a next processing stage, the second latch circuit holding one of a result of the first operation and the first data bypassing the first processing unit through the bypass line as a second data;
• a second instruction decoding unit that determines at least a kind of instruction in the next processing stage, that decodes a second instruction into a third control signal, and that decodes all other instructions with the exception of the second instruction into a fourth control signal as a through instruction upon determining at least the kind of instruction;
• and
• a second processing unit provided in the next processing stage and connected to the second instruction decoding unit, the second processing unit being configured to perform a second operation on the second data when receiving the third control signal, and to pass the second data when receiving the fourth control signal.

A processor execution pipeline, comprising:

• a first instruction decoding unit that determines at least a kind of instruction in a current processing stage, that decodes a first instruction into a first control signal, and that decodes all other instructions with the exception of the first instruction into a second control signal as a through instruction upon determining at least the kind of instruction;
• a first processing unit provided in the current processing stage and connected to the first instruction decoding unit, the first processing unit being configured to perform a first operation on a first data when receiving the first control signal, and to pass the first data when receiving the second control signal;
• a latch circuit provided between the current processing stage and a next processing stage, the latch circuit holding one of a result of the first operation and the first data passing through the first processing unit as a second data;
• a second instruction decoding unit that determines at least a kind of instruction in the next processing stage, that decodes the first instruction into a third control signal, decodes a second instruction into a fourth control signal, and decodes all other instructions with the exception of the first and second instructions into a fifth control signal upon determining at least the kind of instruction;
• a second processing unit provided in the next processing stage and connected to the second instruction decoding unit, the second processing unit being configured to perform a second operation on a second data when receiving the third control signal, and performs a third operation on the second data when receiving the fourth control signal;
• and
• a multiplexer provided in the next processing stage for selecting an output of the second processing unit or the second data held in the latch circuit based on an output of the second instruction decoding unit.

A processor execution pipeline, comprising:

• a first latch circuit provided in a current processing stage for storing a first data;
• a first instruction decoding unit that determines at least a kind of instruction in the current processing stage, that decodes a first instruction into a first control signal, decodes a second instruction into a second control signal, and decodes all other instructions with the exception of the first and second instructions into a third control signal upon determining at least the kind of instruction;
• a first processing unit provided in the current processing stage and connected to the first instruction decoding unit, the first processing unit being configured to perform a first operation on a first data when receiving the first control signal, and performs a second operation on the first data when receiving the second control signal;
• a bypass line provided in parallel with the first processing unit;
• a multiplexer provided in the current processing stage for selecting one of an output of the first processing unit or the first data held in the first latch circuit based on an output of the first instruction decoding unit;
• a second latch circuit provided between the current processing stage and a next processing stage, the second latch circuit holding one of a result of the first operation and the first data bypassing the first processing unit through the bypass line as a second data;
• a second instruction decoding unit provided in the next processing stage, that decodes the first instruction into a fourth control signal, and that decodes all other instructions with the exception of the first instruction into a fifth control signal as a through instruction upon determining at least the kind of instruction;
• and
• a second processing unit provided in the next processing stage and connected to the second instruction decoding unit, the second processing unit being configured to perform a third operation on a second data when receiving the fourth control signal, and to pass the second data when receiving the fifth control signal.

A processor execution pipeline having at least a latching unit to hold and output data, comprising:

• a first instruction decoding unit to convert a first instruction into a first control signal in a current processing stage, and to convert all other instructions with the exception of the first instruction into a second control signal as a through instruction;
• a first processing unit provided in the current processing stage and connected to the first instruction decoding unit, the first processing unit being configured to perform a first operation on a first data when receiving the first control signal, and to pass the first data when receiving the second control signal;
• a latching circuit provided between the current processing stage and a next processing stage, the latch circuit holding one of a result of the first operation and the first data passing the first processing unit as a second data;
• a second instruction decoding unit in the next processing stage to convert a second instruction into a third control signal, and to convert all other instructions with the exception of the second instruction into a fourth control signal;
• a second processing unit provided in the next processing stage and connected to the second instruction decoding unit, the second processing unit being configured to perform a second operation on the second data when receiving the third control signal;
• and
• a multiplexer provided in the next processing stage for selecting an output of the second processing unit or the second data held in the latching circuit based on an output of the second instruction decoding unit;
• wherein the latching unit is configured to be shared by the first processing unit and the second processing unit.