Virtual memory address translation control by TLB purge monitoring
AssigneeHewlett-Packard Development Company, L.P.
InventorTony M. Brewer
Life of this patent
Estimating the term…
Abstract
In a computer system, an architecture is disclosed for optimizing aspects of data movement operations by performing functions such as memory allocation and notification on hardware rather than software. In this environment, the claimed invention is a method and apparatus for ensuring the integrity of data movement operations from virtual memory. The invention monitors and detects Translation Lookaside Buffer (“TLB”) purges, a hardware-based operation whose occurrence signals that virtual-to-physical mapping has changed. Responsive to detection of a TLB purge during the set up or execution of a data movement operation, the claimed invention aborts the operation, and then enqueues corresponding completion status information to notify processors of the event.
Claims16
A method for controlling virtual memory address translation during data movement operations, comprising the steps of:
- monitoring, as a hardware operation, for an occurrence of a translation lookaside buffer (TLB) purge during setup and execution of a data movement operation from virtual memory;
- upon detection of a TLB purge prior to completion of the data movement operation, aborting the data movement operation pending reestablishment of accurate virtual-memory-to-physical-memory mapping;
- and
- enqueuing status information on whether the data movement operation completed or was aborted.
A method for controlling virtual memory address translation during data movement operations enabled in a hardware environment, comprising the steps of:
- monitoring, as a hardware operation, for an occurrence of a translation lookaside buffer (TLB) purge during setup and execution of a data movement operation from virtual memory;
- upon detection of a TLB purge prior to completion of the data movement operation, aborting the data movement operation pending reestablishment of accurate virtual-memory-to-physical-memory mapping;
- and
- enqueuing status information on whether the data movement operation completed or was aborted.
Hardware for controlling virtual memory address translation during data operations involving physical movement of data, the hardware comprising:
- means for setting a first flag upon initiation of a data operation;
- means for periodically monitoring for translation lookaside buffer (TLB) purges;
- means for translating virtual address space to physical address space;
- means for setting up one or more input registers on a data mover;
- means, responsive to said means for translating and said means for setting up, for clearing the first flag if a TLB purge has been detected;
- and
- means for aborting the data operation and then enqueuing a first operation completion status if a TLB purge is detected before physical movement of data is complete.
Dependencies are inferred from the claim text.