Managing processor architected state upon an interrupt
AssigneeInternational Business Machines Corporation
InventorsRavi Kumar Arimilli, Robert Alan Cargnoni, Guy Lynn Guthrie, William John Starke
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Abstract
A method and system are disclosed for managing a hard architected state of a processor that is critical for executing a process in the processor. A shadow copy of the hard architected state is stored from the processor to memory when an interrupt is received by the processor. The shadow copy of the hard architected permits rapid saving of the hard architected state for the interrupted process, so that the architected state of a next process can be immediately stored in the processor.
Claims21
A method of managing state information in a processor, the method comprising:
- storing, within the processor, a current process' hard architected state that is critical for executing a currently executing process in the processor;
- storing, within the processor, a shadow copy of the current process' hard architected state;
- in response to receiving a process interrupt at the processor, storing the shadow copy of the current process' hard architected state in a memory;
- and
- in response to receiving the process interrupt at the processor, replacing the current process' hard architected state with a next process' hard architected state without regard to completion of the storing of the shadow copy in the memory.
A processor comprising:
- at least one execution unit;
- an instruction sequencing unit coupled to the at least one execution unit;
- a first register set coupled to the at least one execution unit, wherein the first register set contains at least a portion of a current process' hard architected state that is critical for executing a currently executing process in the processor;
- a corresponding shadow register set coupled to the first register set, the shadow register set containing a shadow copy of the at least a portion of the current process' hard architected state contained in the first register set;
- and
- a memory controller coupled to the shadow register, wherein the processor, in receipt of a process interrupt, stores the shadow copy of the current process' hard architected state to a memory, and wherein the shadow copy of the current process' hard architected state is stored to the memory without regard to a completion of a replacement of the current process' hard architected state with an architected state for a next process to run on the processor.
A processor comprising:
- means for storing, within the processors, a current process' hard architected state that is critical for executing a currently executing process in the processor;
- means for storing, within the processor, a shadow copy of the current process' hard architected state;
- means, responsive to receiving a process interrupt at the processor, for storing the shadow copy of the current process' hard architected state in a memory;
- and
- means for in response to receiving the process interrupt at the processor, replacing the current process' hard architected state with a next process'hard architected state without regard to completion of the storing of the shadow copy in the memory.
Dependencies are inferred from the claim text.