Memory controlling apparatus performing the writing of data using address line
AssigneeSamsung Electronics Co., Ltd.
InventorHak-su Oh
Life of this patent
Estimating the term…
Abstract
A memory controlling apparatus which receives from an upper module of a system a command to read data from a memory module or write data in the memory module and controls accessing the memory module in response to the command. The memory controlling apparatus includes a first transmitter which transmits an address of read data or write data and the write data to a memory module via an address line; and a second transmitter which transmits data read from a memory module to the upper module of the system via a data line.
Claims28
A memory controlling apparatus comprising:
- a memory module;
- an address line;
- a data line;
- a first transmitter which transmits an address of read data, and an address of write data along with the write data to the memory module via the address line;
- and
- a second transmitter which transmits data read from the memory module via the data line.
A memory controlling apparatus comprising:
- a memory module;
- an address line;
- a data line;
- a first transmitter which transmits an address of read data, or an address of write data along with the write data to the memory module via the address line;
- and
- a second transmitter which transmits data read from the memory module via the data line,
- wherein the first transmitter's transmission of an address of read data, or an address of write data along with the write data to the memory module via the address line, and the second transmitter's transmission of data read from the memory module via the data line are performed contemporaneously without causing a data bottleneck.
A memory controlling apparatus comprising:
- a memory module;
- an address line;
- a data line;
- a first transmitter which transmits an address of read data, or an address of write data along with the write data to the memory module via the address line;
- and
- a second transmitter which transmits data read from the memory module via the data line,
- wherein the read data and the write data are transmitted at both up and down edges of a clock signal.
A memory controlling apparatus comprising:
- a memory module;
- an address line;
- a data line;
- a first transmitter which transmits an address of read data, or an address of write data along with the write data to the memory module via the address line;
- and
- a second transmitter which transmits data read from the memory module via the data line,
- wherein the first transmitter comprises an address queue which sequentially stores the address of the read data, or the address of the write data and the write data, and keeps the stored address and the stored data in a state ready to be transmitted to the memory module.
A memory controlling apparatus comprising:
- a memory module;
- an address line;
- a data line;
- a first transmitter which transmits an address of read data, or an address of write data along with the write data to the memory module via the address line;
- and
- a second transmitter which transmits data read from the memory module via the data, wherein:
- the first transmitter comprises an address queue, wherein when writing the write data,
- the memory controlling apparatus stores the address of the write data in the address queue,
- then stores the write data in the address queue, and
- then sequentially transmits the stored address and the stored data to the memory module via the address line.
A memory controlling apparatus which receives, from an upper module of a system, a command to read data from a memory module or to write data in the memory module, and controls accessing the memory module in response to the command, the memory controlling apparatus comprising:
- an address line;
- a data line;
- an address latch which latches address data;
- a data latch which latches read data or write data;
- an address and write data queue which;
- sequentially stores,
- an address, input from the address latch, and
- the write data, from the data latch, and
- transmits the stored address and the stored data to the memory module via the address line;
- and
- a data queue which sequentially stores the read data, input from the memory module via the data line, and transmits the read data to the upper module.
A memory controlling apparatus which receives, from an upper module of a system, a command to read data from a memory module or to write data in the memory module, and controls accessing the memory module in response to the command, the memory controlling apparatus comprising:
- an address line;
- a data line;
- an address latch which latches address data;
- a data latch which latches read data or write data;
- an address queue which stores an address input from the address latch and transmits the stored address to the memory module via the address line;
- a write data queue which stores the write data input from the data latch and sequentially transmits the stored write data to the memory module via the address line;
- and
- a read data queue which sequentially stores the read data input from the memory module via the data line and transmits the read data to the upper module.
A memory controlling apparatus comprising:
- an address line;
- a data line;
- a memory;
- a memory controller which transmits an address and write data via the address line and receives read data via the data line;
- and
- a memory module comprising:
- a memory buffer;
- and
- a write data buffer;
- wherein the memory module:
- separates an address from the write data;
- transmits the address to the memory buffer and the write data to the write data buffer;
- writes the data on a memory cell indicated by the address;
- and
- transmits data read from the memory to the memory controller via the data line.
A memory controlling apparatus comprising:
- a memory module;
- a memory controller;
- a first transmission line, which transmits column address, row address, and/or write data from the memory controller to the memory module, and which does not transmit read data from the memory module;
- and
- a second transmission line, which transmits only read data from the memory module to the memory controller.
A memory controlling apparatus which receives, from an upper module of a system, a command to read data from a memory module or to write data in the memory module, and controls accessing the memory module in response to the command, the memory controlling apparatus comprising:
- an address line, which transmits column address, row address, and/or write data to the memory module, and which does not transmit read data from the memory module;
- and
- a data line, which transmits only read data from the memory module.
Dependencies are inferred from the claim text.