Mitigating access penalty of a semiconductor nonvolatile memory
AssigneeIntel Corporation
InventorJohn C. Rudelic
Life of this patent
Estimating the term…
Abstract
Adding a nonvolatile storage (e.g., a cache) to an associated memory array within a semiconductor nonvolatile memory may mitigate the access penalty that occurs in semiconductor nonvolatile memories, such as flash memories and flash devices. For example, in response to a memory access request, the cache may be accessed for data before accessing the memory array and the data may be selectively stored from the memory array into the cache. In another embodiment, an asynchronous access to a semiconductor nonvolatile memory may be converted into a synchronous access.
Claims34
A method comprising:
- determining whether a memory access is asynchronous to a signal;
- and
- caching data for a semiconductor nonvolatile memory in a cache memory from an associated memory array based at least in part on whether a memory access is asynchronous.
A method comprising:
- using within a semiconductor nonvolatile memory a flash cache memory separate from an associated memory array to cache frequently accessed data;
- determining whether a memory access is asynchronous to a signal;
- in response to an asynchronous memory access, storing data into the cache memory returned from the memory array of said semiconductor nonvolatile memory;
- determining whether an address location storing said data is available in the cache memory;
- and
- if the address location is available, converting said asynchronous memory access into a synchronous memory access being coincident with the system clock.
An apparatus comprising:
- a semiconductor nonvolatile memory including a cache memory separately accessible from an associated memory array to determine whether a memory array access is asynchronous to a signal and, if so, to store data at said semiconductor nonvolatile memory from the memory array into the cache memory.
A semiconductor nonvolatile memory comprising:
- a cache including one or more cache entries to receive data based, at least in part, on whether a read request is asynchronous.
A processor-based system comprising:
- a processor;
- and
- a flash device operably couplable to said processor, said flash device including a cache memory separately accessible from an associated flash memory array at said semiconductor nonvolatile memory depending on whether a memory read request is asynchronous to a signal and, if so, causing a selective storing of data from the memory array into the cache memory.
An article comprising a medium storing instructions that, when executed by a processor-based system result in:
- determining whether a memory access is asynchronous to a signal:
- and
- caching data for a semiconductor nonvolatile memory in a cache memory from an associated memory array depending on whether a memory access is asynchronous.
An article comprising a medium storing instructions that, when executed by a processor-based system result in:
- using within a semiconductor nonvolatile memory a cache memory separate from an associated memory array to cache frequently accessed data;
- determining whether a memory access is asynchronous to a signal;
- in response to an asynchronous memory access, storing data into the cache memory returned from the memory array of said semiconductor nonvolatile memory;
- determining whether an address location storing said data is available in the cache memory;
- if the address location is available, converting said asynchronous memory access into a synchronous memory access being coincident with the system clock;
- monitoring access to the cache memory;
- and
- in response to said monitoring, determining at least one selected asynchronous memory access based, at least in part, on access penalty of said semiconductor nonvolatile memory.
A processor-based system comprising:
- a digital signal processor;
- a semiconductor nonvolatile memory coupled to said digital signal processor, said semiconductor nonvolatile memory including a cache memory separately accessible from an associated memory array at said semiconductor nonvolatile memory depending on whether a system read request is asynchronous to a signal and, if so, causing a selective storing of data from said memory array into the cache memory;
- and
- a wireless interface coupled to said digital signal processor to enable wireless communications.
Dependencies are inferred from the claim text.