DRAM with hidden refresh
AssigneeMicron Technology, Inc.
InventorKevin J. Ryan
Life of this patent
Estimating the term…
Abstract
A synchronous DRAM is provided having specified time slots (e.g., every multiple of 4 clock pulses of a DRAM input clock) within which read or write commands may be entered on the command/address bus. During operation, the DRAM performs internally generated refresh operations on a periodic basis while avoiding collisions with controller-generated data accesses. An internal refresh cycle can be executed without interfering with any data accesses by starting the refresh after decoding a non-conflicting command in one of these time slots and finishing before the next command time slot. If an internal refresh operation is delayed (e.g., by the decoding of a conflicting access command) it will be completed at the earliest opportunity thereafter.
Claims28
A method for refreshing memory cells, comprising:
- determining that a data access command has been applied to a command/address bus at a first predetermined time slot for applying data access commands;
- determining that said data access command conflicts with a refresh;
- completing a first data access commanded by said conflicting data access command;
- waiting for a next available time slot during which said refresh may be initiated;
- determining whether a second data access command has been applied to said command/address bus at a second predetermined time slot for applying data access commands;
- and
- initiating said refresh during said next available time period and prior to reaching a third predetermined time slot for applying data access commands without conflicting with a second data access commanded by said second data access command.
A system for refreshing memory cells of a dynamic random access memory (DRAM) comprising:
- a memory array containing said memory cells;
- a second memory source other than said memory cells;
- a communication link for respectively delivering data access commands to said DRAM on a plurality of predetermined time slots, said plurality of predetermined time slots defining the only time slots on said communication link during which said data access commands may be placed on said communication link;
- and
- a controller for operating said memory array in accordance with said data access commands, wherein
- said controller is configured to initiate a refresh at a predetermined time and without delaying a data access triggered by a data access command, and wherein
- said controller operates said DRAM such that a conflicting data access command is satisfied with said second memory source other than said memory cells and wherein said memory cells may be refreshed.
A memory device, comprising:
- a memory controller configured to operate said memory device to:
- determine that a data access command has been applied to a command/address bus at a first predetermined time slot for applying data access commands;
- determine that said data access command conflicts with a refresh;
- complete a first data access commanded by said conflicting data access command;
- wait for a next available time slot during which said refresh may be initiated;
- determine whether a second data access command has been applied to said command/address bus at a second predetermined time slot for applying data access commands;
- and
- initiate said refresh during said next available time period and prior to reaching a third predetermined time slot for applying data access commands without conflicting with a second data access commanded by said second data access command.
A processor-based system, comprising:
- a processor;
- and
- a dynamic random access memory (DRAM) coupled to said processor, said dynamic random access memory having a system for refreshing memory cells in said dynamic random access memory, said system comprising:
- a memory array containing said memory cells;
- a second memory source other than said memory cells;
- a communication link for respectively delivering data access commands to said DRAM on a plurality of predetermined time slots, said plurality of predetermined time slots defining the only time slots on said communication link during which said data access commands may be placed on said communication link;
- and
- a controller for operating said memory array in accordance with said data access commands, wherein
- said controller is configured to initiate a refresh at a predetermined time and without delaying a data access triggered by a data access command, and wherein
- said controller operates said DRAM such that a conflicting data access command is satisfied with said second memory source other than said memory cells and wherein said memory cells may be refreshed.
Dependencies are inferred from the claim text.