Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing
AssigneeRenesas Technology Corp.
InventorYuichi Kunori
Life of this patent
Estimating the term…
Abstract
A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence of 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.
Claims29
A nonvolatile semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged therein,
- each said memory cell including a storage element holding binary data of n bits based on 2n (n:
- natural number) threshold levels, and
- said threshold levels respectively corresponding to ordered data obtained by rearranging a data set of said binary data of n bits in a procedure equivalent to steps of:
- i) associating n bit pointer variables BP(i) (i:
- natural number, 1≦i≦n) with n integers from zero to (n−1) arranged in arbitrary order respectively,
- ii) dividing said data set into two data groups according to whether data of a BP(1)-th bit is “0” or “1” and arranging said two data groups in order in a first step, and
- iii) dividng each of said data groups of said data set, which has been divided into 2j−1 groups in the process up to a (j−1)th step, into two data groups further in response to whether data of a BP(j)-th bit is “0” or “1” in a j-th step (j:
- natural number, 2≦j=n);
- a cell selection circuit collectively selecting a plurality of said memory cells from said memory cell array in response to an address signal;
- a data read/write circuit performing a read/write operation of storage data on said selected plurality of memory cells on the basis of (2n−1) determination levels corresponding to boundaries between groups of said threshold levels corresponding to said data groups;
- and
- a data input/output circuit for transferring said storage data between the outside of said nonvolatile semiconductor memory device and said memory cells as binary data through k input/output nodes by every k bit (k:
- natural number), wherein
- storage data held in each said memory cell is generated from n bit data transferred at different timings through the same said input/output node.
A method for reading a plurality of data from a non-volatile semiconductor memory device, said non-volatile semiconductor memory device including a memory cell storing said plurality of data, a read circuit reading said data by selecting a word line connected to said memory cell, and a data output node for outputting said data read by said read circuit, said method comprising the steps of:
- reading a part of said plurality of data from said memory cell by selecting said word line;
- outputting said part of said plurality of data to said data output node;
- reading another part of said plurality of data from said memory cell by selecting said word line;
- and
- outputting said another part of said plurality of data to said data output node, wherein
- said step of outputting said part of said plurality of data overlaps with said step of reading another part of said plurality of data.
A method for reading data from a non-volatile semiconductor memory device, said non-volatile semiconductor memory device including
- a word line,
- first and second bit lines,
- a first memory cell coupled to said word line and said first bit line,
- a second memory cell coupled to said word line and said second bit line, and
- a data output node for outputting said data from said first and second memory cells, said method comprising the steps of:
- reading first data from said first memory cell with selectively activating said word line;
- outputting said first data to said data output node;
- reading second data from said second memory cell with selectively activating said word line;
- and
- outputting said second data to said data output node, wherein
- said step of outputting said first data overlaps with said step of reading second data.
A method for writing data to a non-volatile semiconductor memory device, said non-volatile semiconductor memory device including a memory cell storing first and second data, and first and second registers, said method comprising the steps of:
- storing in said first register said first data input from the outside of said non-volatile semiconductor memory device;
- writing said first data stored in said first register to said memory cell;
- storing in said second register said second data input from the outside of said non-volatile semiconductor memory device;
- and
- writing said second data stored in said second register to said memory cell to which said first data has been already written,
- wherein said step of writing said first data overlaps with said step of storing said second data.
A nonvolatile semiconductor memory device comprising:
- a memory cell array having a plurality of memory cells arranged therein, each said memory cell including a storage element holding binary data of 2 bits based on 22 threshold levels, wherein
- said threshold levels corresponds to elements “11”, “10”, “00” and “01” forming a set of 2-bit data respectively in ascending order;
- a cell selection circuit collectively selecting a plurality of said memory cells from said memory cell array in response to an address signal;
- a data read circuit performing a read operation of storage data on said selected plurality of memory cells on the basis (22−1) determination levels corresponding to boundaries between said threshold levels;
- and
- a data input/output circuit for transferring said storage data between the outside of said nonvolatile semiconductor memory device and said memory cells as binary data through k input/output nodes by every k bit (k:
- natural number), wherein
- storage data held in each said memory cell is generated from 2 bit data transferred at different timings through the same said input/output node, wherein
- said data read circuit determines first determination data based on 2nd one of said determination levels to identify the data of 2nd bit in said storage data held in said storage elements, and determines second determination data based on 1st and 3rd ones of said determination levels to perform an operation on said second determination data for identification of the data of 1st bit in said storage data.
Dependencies are inferred from the claim text.